Semiconductor memory device having an electrically floating body transistor

• US 8,817,548 B2
• Filed: 09/05/2013
• Issued: 08/26/2014
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/018,947
• Publication Number:
  US 20140042503A1
• Time in Patent Office: 355 Days
• Field of Search: 365/189.011, 365/189.04, 365/149
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

Claims

1. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region, located at a surface of said floating body region; and

a buried region in electrical contact with said floating body region, located below said floating body region;

wherein said buried region is commonly connected to at least two of said semiconductor memory cells in said matrix; and

wherein an electrical signal applied to said buried region is of different amplitude or polarity, depending on an operation performed on said memory cell.

2. The semiconductor memory array of claim 1, wherein each of said memory cells further comprises a region of a first conductivity type at the surface.

3. The semiconductor memory array of claim 1, wherein each of said memory cells further comprises a gate region above the surface and an insulating layer insulating the gate region from the surface.

4. The semiconductor memory array of claim 1, wherein each of said memory cells further comprises a well region of a second conductivity type beneath the buried region.

5. The semiconductor memory array of claim 1, wherein said electrical signal applied to said buried region comprises a pulse.

6. The semiconductor memory array of claim 1, wherein said electrical signal applied to said buried region comprises a constant amplitude level.

7. A semiconductor memory cell comprising:

a bipolar device having a floating base region, a first region, and a second region, wherein;

a state of said memory cell is stored in said floating base region;

said first region is located at the surface of said floating base region;

said second region is located below said floating base region; and

wherein said second region is discontinuous along one direction.

8. The semiconductor memory cell of claim 7, further comprising a gate above the surface and an insulating layer insulating the gate from the surface.

9. The semiconductor memory cell of claim 7, wherein said second region is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of said memory cell.

10. The semiconductor memory cell of claim 7, wherein said memory cell further comprises a well region of a first conductivity type beneath a buried region.

11. The semiconductor memory cell of claim 9, wherein said electrical signal applied to a buried region comprises a pulse.

12. The semiconductor memory cell of claim 9, wherein said electrical signal applied to a buried region comprises a constant amplitude level.

13. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns wherein each said semiconductor memory cell includes;

a bipolar device having a floating base region, a first region, and a second region, wherein;

a state of said semiconductor memory cell is stored in said floating base region;

said first region is located at the surface of said floating base region;

said second region is located below said floating base region;

wherein said second region is commonly connected to at least two of said semiconductor memory cells in said matrix; and

wherein said second region is discontinuous along one direction.

14. The semiconductor memory array of claim 13, further comprising a gate above the surface and an insulating layer insulating the gate from the surface.

15. The semiconductor memory array of claim 13, wherein each of said second regions is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.

16. The semiconductor memory array of claim 13, wherein each of said memory cells further comprises a well region of a first conductivity type beneath a buried region.

17. The semiconductor memory array of claim 16, wherein an electrical signal applied to said buried region comprises a pulse.

18. The semiconductor memory array of claim 16, wherein an electrical signal applied to said buried region comprises a constant amplitude level.