Configurable multirank memory system with interface circuit

• US 8,819,356 B2
• Filed: 09/14/2012
• Issued: 08/26/2014
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Wang, David T.
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US13/620,207
• Publication Number:
  US 20130117495A1
• Time in Patent Office: 711 Days
• Field of Search: 711/154, 711/167
• US Class Current: 711/154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An interface circuit that is configured to receive a first read command from a memory controller to read first data stored in a first memory circuit and a second read command to read second data that is stored in a second memory circuit, and transmit the first data and the second data to the memory controller across a data bus without a delay on the data bus between the first data and the second data.

Claims

1. A memory module comprising:

a first rank of memory circuits comprising a first memory circuit;

a second rank of memory circuits comprising a second memory circuit;

an interface circuit;

a first data bus that connects to the first memory circuit, the second memory circuit, and the interface circuit, the first data bus having a first data bus width; and

a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is narrower than the first data bus width;

wherein the interface circuit is operable to;

receive a first read command from the memory controller to read first data stored in the first memory circuit;

after receiving the first read command, receive a second read command from the memory controller to read second data that is stored in the second memory circuit;

enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus;

read the first data from the first memory circuit across the first data bus;

transmit the first data to the memory controller across the second data bus;

insert idle clock cycles, and during the idle clock cycles;

(i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and

(ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus;

read the second data from the second memory circuit across the first data bus; and

transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data.

2. The memory module of claim 1, wherein the interface circuit is further operable to:

receive a first write command from the memory controller to write first data to the first memory circuit;

after receiving the first write command, receive a second write command from the memory controller to write second data to the second memory circuit;

receive the first write data across the second data bus from the memory controller;

receive the second write data across the second data bus from the memory controller, wherein the first write data and the second write data are received by the interface circuit without a delay on the second data bus between the first write data and the second write data;

enable the chip select pin of the first memory circuit to connect the first memory circuit to the first data bus;

transmit the first write data to the first memory circuit across the first data bus;

insert idle clock cycles, and during the idle clock cycles;

(i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and

(ii) enable the chip select pin of the second memory circuit to connect the second memory circuit to the first data bus; and

transmit the second write data to the second memory circuit across the first data bus.

3. The memory module of claim 1, wherein the interface circuit is further operable to insert idle clock cycles in a burst chop mode.

4. The memory module of claim 1, wherein the memory circuits in the first rank and the second rank are x8 memory circuits, and wherein the interface circuit is further operable to present the memory module to the memory controller as a memory module with x4 memory circuits.

5. The memory module of claim 1, further comprising:

a non-volatile memory circuit that stores configuration and capabilities of the memory module to be presented to the memory controller, wherein the interface circuit is further operable to modify the configuration and capabilities stored on the non-volatile memory circuit.

6. The memory module of claim 1, wherein the second data bus width is half of the first data bus width.

7. The memory module of claim 1, wherein the delay is an intra-DIMM rank-rank turnaround time.

8. A sub-system comprising:

an interface circuit;

a first memory module comprising;

a first rank of memory circuits comprising a first memory circuit;

a second memory module comprising;

a second rank of memory circuits comprising a second memory circuit;

a first data bus that connects to the first memory module, the second memory module, and the interface circuit, the first data bus having a first data bus width; and

a second data bus that connects to the interface circuit and a memory controller, the second data bus having a second data bus width, wherein the second data bus width is narrower than the first data bus width;

wherein the interface circuit is operable to;

receive a first read command from the memory controller to read first data stored in the first memory circuit;

after receiving the first read command, receive a second read command from the memory controller to read second data that is stored in the second memory circuit;

enable a chip select pin of the first memory circuit to connect the first memory circuit to the first data bus;

read the first data from the first memory circuit across the first data bus;

transmit the first data to the memory controller across the second data bus;

insert idle clock cycles, and during the idle clock cycles;

(i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and

(ii) enable a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus;

read the second data from the second memory circuit across the first data bus; and

transmit the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data.

9. The sub-system of claim 8, wherein the interface circuit is further operable to:

receive a first write command from the memory controller to write first data to the first memory circuit;

after receiving the first write command, receive a second write command from the memory controller to write second data to the second memory circuit;

receive the first write data across the second data bus from the memory controller;

receive the second write data across the second data bus from the memory controller, wherein the first write data and the second write data are received by the interface circuit without a delay on the second data bus between the first write data and the second write data;

enable the chip select pin of the first memory circuit to connect the first memory circuit to the first data bus;

transmit the first write data to the first memory circuit across the first data bus;

insert idle clock cycles, and during the idle clock cycles;

(i) disable the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and

(ii) enable the chip select pin of the second memory circuit to connect the second memory circuit to the first data bus; and

transmit the second write data to the second memory circuit across the first data bus.

10. The sub-system of claim 8, wherein the interface circuit is further operable to insert idle clock cycles in a burst chop mode.

11. The sub-system of claim 8, wherein the memory circuits in the first rank and the second rank are x8 memory circuits, and wherein the interface circuit is further operable to present the first memory module and the second memory module to the memory controller as memory modules with x4 memory circuits.

12. The sub-system of claim 8, further comprising:

a non-volatile memory circuit that stores configuration and capabilities of the first memory module and the second memory module to be presented to the memory controller, wherein the interface circuit is further operable to modify the configuration and capabilities stored on the non-volatile memory circuit.

13. The sub-system of claim 8, wherein the second data bus width is half of the first data bus width.

14. The sub-system of claim 8, wherein the delay is an inter-DIMM rank-rank turnaround time.

15. A computer-implemented method, comprising:

receiving, from a memory controller by an interface circuit, a first read command to read first data stored in a first memory circuit;

after receiving the first read command, receiving a second read command from the memory controller to read second data that is stored in a second memory circuit;

enabling a chip select pin of the first memory circuit to connect the first memory circuit to a first data bus, wherein the first data bus is connected to the first memory circuit, the second memory circuit, and the interface circuit, and wherein the first data bus has a first data bus width;

reading the first data from the first memory circuit across the first data bus;

transmitting the first data to the memory controller across a second data bus, wherein the second data bus is connected to the interface circuit and the memory controller, wherein the second data bus has a second data bus width that is narrower than the first data bus width;

inserting idle clock cycles, and during the idle clock cycles;

(i) disabling the chip select pin of the first memory circuit to disconnect the first memory circuit from the first data bus, and

(ii) enabling a chip select pin of the second memory circuit to connect the second memory circuit to the first data bus, while the first data is being transmitted to the memory controller across the second data bus;

reading the second data from the second memory circuit across the first data bus; and

transmitting the second data to the memory controller across the second data bus without a delay on the second data bus between the first data and the second data.

16. The method of claim 15, wherein inserting idle clock cycles further comprises inserting the idle clock cycles in a burst chop mode.

17. The method of claim 15, wherein the second data bus width is half of the first data bus width.

18. The method of claim 15, wherein the delay is an intra-DIMM rank-rank turnaround time.

19. The method of claim 15, wherein the delay is an inter-DIMM rank-rank turnaround time.

20. The method of claim 15, further comprising:

modifying configuration and capabilities stored on a non-volatile memory circuit, wherein the non-volatile memory circuit stores the configuration and the capabilities of the first memory circuit and the second memory circuit to be presented to the memory controller.