Control flow management for execution of dynamically translated non-native code in a virtual hosting environment

• US 8,819,648 B2
• Filed: 07/20/2012
• Issued: 08/26/2014
• Est. Priority Date: 07/20/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brown, Alexander Barraclough
• Primary Examiner(s): Khatri, Anil
• Application Number:
  US13/554,141
• Publication Number:
  US 20140025893A1
• Time in Patent Office: 767 Days
• Field of Search: 717126-129, 717131-143, 717147-148
• US Class Current: 717/136
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/45516 Runtime code conversion or optimisation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

Execution of non-native operating system images within a virtualized computer system is improved by providing a mechanism for retrieving translated code physical addresses corresponding to un-translated code branch target addresses using a host code map. Hardware acceleration mechanisms, such as content-accessible look-up tables, directory hardware, or processor instructions that operate on tables in memory can be provided to accelerate the performance of the translation mechanism. The virtual address of the branch instruction target is used as a key to look up a corresponding record that contains a physical address of the translated code page containing the translated branch instruction target, and execution is directed to the physical address obtained from the record, once the physical page containing the translated code corresponding the target address is loaded in memory.

Claims

1. A computer-performed method for hosting guest program code having a non-native instruction set executing within a host operating system within a virtualized computer system, the method comprising:

dynamically translating the guest program code to translated native program code;

caching pages of the translated native program code in a translated native code page cache;

executing the translated native program code;

detecting that a portion of the translated native program code corresponding to a non-native branch instruction will cause the executing to be directed to a particular translated code physical address corresponding to a particular non-native virtual address in a different first non-native virtual memory page than a second non-native virtual memory page containing the non-native branch instruction;

responsive to detecting that the program control instruction will cause the executing to be directed to the particular translated code physical address, retrieving a record indicating a location of a translated code page containing the particular translated code physical address using the particular non-native virtual address as a key into a host code map that directly maps non-native virtual addresses to translated code physical addresses, wherein the retrieving comprises adding the particular non-native virtual address to a base address of the host code map to obtain a pointer into the host code map corresponding to an address at which the record is stored and de-referencing the pointer to obtain the record;

loading the translated code page into physical memory; and

directing the executing to the particular translated code physical address in the translated code page.

2. The computer-performed method of claim 1, further comprising:

determining whether or not the pointer is a null pointer; and

responsive to determining that the pointer is a null pointer, directing the dynamically translating to translate the translated code page, wherein the pointer being the null pointer indicates the translated code page has not yet been translated.

3. The computer-performed method of claim 1, wherein the de-referencing results in a page fault indicating the record is not present in the host code map, and wherein the method further comprises causing the dynamically translating to resolve the particular non-native virtual address to an address of the translated code page.

4. The computer-performed method of claim 1, wherein the pointer is a first pointer that points to a record containing a second pointer corresponding to the particular translated code physical address.

5. The computer-performed method of claim 4, wherein the second pointer is compressed to permit the host code map to store pointers larger than pointers in a native instruction set of the host operating system, and wherein the retrieving further comprises uncompressing the second pointer.

6. The computer-performed method of claim 1, wherein the dynamically translating further comprises:

detecting that a branch instruction within the guest program code has the particular non-native virtual address lying outside of a code page containing the branch instruction; and

populating the host code map from entries in a guest data structure representative of a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.

7. The computer-performed method of claim 1, further comprising:

performing a context switch that takes the guest program code off-line; and

storing an image of the guest program code, wherein the host code map is automatically stored within the image of the guest program code by the storing.

8. The computer-performed method of claim 1, further comprising populating the host code map according to a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.

9. A computer system comprising a processor for executing program instructions and a memory coupled to the processor for executing the program instructions, wherein the program instructions implement a host operating system hosting guest program code having a non-native instruction set within a virtual processing machine instance executing within the computer system, wherein the program instructions comprise program instructions for:

dynamically translating the guest program code to translated native program code;

caching pages of the translated native program code in a translated native code page cache;

executing the translated native program code;

detecting that a portion of the translated native program code corresponding to a non-native branch instruction will cause the executing to be directed to a particular translated code physical address corresponding to a particular non-native virtual address in a different first non-native virtual memory page than a second non-native virtual memory page containing the non-native branch instruction;

responsive to detecting that the program control instruction will cause the executing to be directed to the particular translated code physical address, retrieving a record indicating a location of a translated code page containing the particular translated code physical address using the particular non-native virtual address as a key into a host code map that directly maps non-native virtual addresses to translated code physical addresses, wherein the program instructions for retrieving comprise program instructions for adding the particular non-native virtual address to a base address of the host code map to obtain a pointer into the host code map corresponding to an address at which the record is stored and de-referencing the pointer to obtain the record;

loading the translated code page into physical memory; and

directing the executing to the particular translated code physical address in the translated code page.

10. The computer system of claim 9, wherein the program instructions further comprise program instructions for:

determining whether or not the pointer is a null pointer; and

responsive to determining that the pointer is a null pointer, directing the dynamically translating to translate the translated code page, wherein the pointer being the null pointer indicates the translated code page has not yet been translated.

11. The computer system of claim 9, wherein execution of the program instructions for de-referencing results in a page fault indicating the record is not present in the host code map, and wherein the program instructions further comprise program instructions for causing the dynamically translating to resolve the particular non-native virtual address of the translated branch instruction target to an address of the translated code page.

12. The computer system of claim 9, wherein the pointer is a first pointer that points to a record containing a second pointer corresponding to the translated code physical address.

13. The computer system of claim 12, wherein the second pointer is compressed to permit the host code map to store pointers larger than pointers in a native instruction set of the host operating system, and wherein the program instructions for retrieving further comprise program instructions for uncompressing the second pointer.

14. The computer system of claim 9, wherein the program instructions for dynamically translating further comprise program instructions for:

detecting that a branch instruction within the guest program code has the particular non-native virtual address lying outside of a code page containing the branch instruction; and

populating the host code map from entries in a guest data structure representative of a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.

15. The computer system of claim 9, wherein the program instructions further comprise program instructions for:

performing a context switch that takes the guest program code off-line; and

storing an image of the guest program code, wherein the host code map is automatically stored within the image of the guest program code by the storing.

16. The computer system of claim 9, wherein the program instructions further comprise program instructions for populating the host code map according to a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.

17. A computer program product comprising a computer-readable storage device storing program instructions for execution within a computer system, wherein the program instructions implement a host operating system for hosting guest program code having a non-native instruction set within a virtual processing machine instance within the computer system, wherein the program instructions comprise program instructions for:

dynamically translating the guest program code to translated native program code;

caching pages of the translated native program code in a translated native code page cache;

executing the translated native program code;

detecting that a portion of the translated native program code corresponding to a non-native branch instruction will cause the executing to be directed to a particular translated code physical address corresponding to a particular non-native virtual address in a different first non-native virtual memory page than a second non-native virtual memory page containing the non-native branch instruction;

responsive to detecting that the program control instruction will cause the executing to be directed to the particular translated code physical address, retrieving a record indicating a location of a translated code page containing the particular translated code physical address using the particular non-native virtual address as a key into a host code map that directly maps non-native virtual addresses to translated code physical addresses, wherein the program instructions for retrieving comprise program instructions for adding the particular non-native virtual address to a base address of the host code map to obtain a pointer into the host code map corresponding to an address at which the record is stored and de-referencing the pointer to obtain the record;

loading the translated code page into physical memory; and

directing the executing to the particular translated code physical address in the translated code page.

18. The computer program product of claim 17, wherein the program instructions further comprise program instructions for:

determining whether or not the pointer is a null pointer; and

responsive to determining that the pointer is a null pointer, directing the dynamically translating to translate the translated code page, wherein the pointer being the null pointer indicates the translated code page has not yet been translated.

19. The computer program product of claim 17, wherein execution of the program instructions for de-referencing results in a page fault indicating the record is not present in the host code map, and wherein the program instructions further comprise program instructions for causing the dynamically translating to resolve the particular non-native virtual address to an address of the translated code page.

20. The computer program product of claim 17, wherein the pointer is a first pointer that points to a record containing a second pointer corresponding to the translated code physical address.

21. The computer program product of claim 20, wherein the second pointer is compressed to permit the host code map to store pointers larger than pointers in a native instruction set of the host operating system, and wherein the program instructions for retrieving further comprise program instructions for uncompressing the second pointer.

22. The computer program product of claim 17, wherein the program instructions for dynamically translating further comprise program instructions for:

detecting that a branch instruction within the guest program code has the particular non-native virtual address lying outside of a code page containing the branch instruction; and

populating the host code map from entries in a guest data structure representative of a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.

23. The computer program product of claim 17, wherein the program instructions further comprise program instructions for:

performing a context switch that takes the guest program code off-line; and

storing an image of the guest program code, wherein the host code map is automatically stored within the image of the guest program code by the storing.

24. The computer program product of claim 17, wherein the program instructions further comprise program instructions for populating the host code map according to a virtual to physical memory map of an operating system hosting the guest program code such that only entries corresponding to the pages of the translated native program code that contain target addresses of corresponding non-native branch instructions that have target addresses in different virtual address pages from their corresponding non-native branch instructions are stored in the host code map.