Method of manufacturing stacked resonated coil

• US 8,819,920 B2
• Filed: 09/06/2012
• Issued: 09/02/2014
• Est. Priority Date: 09/27/2011
• Status: Expired due to Fees

• Current Assignee: Wit Co., Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Yoon, Young Seok, Kim, Eung Ju
• Primary Examiner(s): PHAN, THIEM D
• Application Number:
  US13/605,807
• Publication Number:
  US 20130074321A1
• Time in Patent Office: 726 Days
• Field of Search: 296/021, 29/254.2, 298/25, 298/29, 298/32, 298/46, 340/571, 340/572.1, 340/572.5, 340/572.7, 340/572.8
• US Class Current: 29/602.1
• CPC Class Codes: H01F 27/006 with special arrangement or spacing of turns of the winding(s), e.g. to produce desired self-resonance
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

Disclosed herein is a method of manufacturing a stacked resonant coil, the method including: (A) forming circuit layers on a plurality of double-sided FCCLs, respectively, and then stacking the double-sided FCCLs respectively having the circuit layers formed thereon; (B) forming first and second conductive via holes in the stacked plurality of double-sided FCCLs, the first conductive via hole being for interlayer connection of the first ends respectively formed in the circuit layers and the second conductive via hole being for interlayer connection of the first electrode patterns respectively formed in the circuit layers; and (C) forming a wiring layer on an external layer of an uppermost double-sided FCCL in the staked plurality of double-sided FCCLs, the wiring layer electrically connecting the first ends and the first electrode patterns, thereby improving mass-productivity of products having uniform performances and excellent quality.

Claims

1. A method of manufacturing a stacked resonant coil, the method comprising:

(A) forming circuit layers on a plurality of double-sided FCCLs, respectively, and then stacking the double-sided FCCLs respectively having the circuit layers formed thereon by using a first adhesive, each of the circuit layers including a coil pattern, first and second ends of the coil pattern, a first electrode pattern, and a second electrode pattern formed integrally with the second end;

(B) forming first and second conductive via holes in the stacked plurality of double-sided FCCLs, the first conductive via hole being for interlayer connection of the first ends respectively formed in the circuit layers and the second conductive via hole being for interlayer connection of the first electrode patterns respectively formed in the circuit layers; and

(C) forming a wiring layer on an external layer of an uppermost double-sided FCCL in the staked plurality of double-sided FCCLs, the wiring layer connecting between the first and second conductive via holes for electrically connecting the first ends and the first electrode patterns.

2. The method as set forth in claim 1, wherein the stage (A) includes:

(A-1) etching a first surface of a first double-sided FCCL to form a first circuit layer including a coil pattern, first and second ends of the coil pattern, a first electrode pattern, and a second electrode pattern formed integrally with the second end;

(A-2) etching a second surface of a second double-sided FCCL to form a second circuit layer corresponding to the first circuit layer, the second circuit layer including a coil pattern, first and second ends of the coil pattern, a first electrode pattern, and a second electrode pattern formed integrally with the second end; and

(A-3) disposing the first adhesive between the first and second circuit layers, followed by pressing.

3. The method as set forth in claim 1, wherein the stage (B) includes:

(B-1) forming the first conductive via hole for interlayer connection of the first ends respectively formed in the circuit layers of the stacked plurality of double-sided FCCLs; and

(B-2) forming the second conductive via hole for interlayer connection of the first electrode patterns respectively formed in the circuit layers of the stacked plurality of double-sided FCCLs.

4. The method as set forth in claim 1, wherein the stage (C) includes:

(C-1) plating insides of the first and second conductive via holes;

(C-2) plating the external layer of the uppermost double-sided FCCL and an external layer of a lowermost double-sided FCCL in the stacked plurality of double-sided FCCLs, to thereby form first and second plating layers; and

(C-3) etching the first plating layer and the external layer of the uppermost double-sided FCCL such that the first and second conductive via holes are connected to each other, to thereby form the wiring layer crossing from the first conductive via hole to the second conductive via hole.

5. The method as set forth in claim 4, wherein the stage (C) further includes (C-4) etching the second plating layer and the external layer of the lowermost FCCL to thereby form a circuit layer including a coil pattern, first and second ends of the coil pattern, a first electrode pattern, and a second electrode pattern formed integrally with the second end.

6. The method as set forth in claim 1, further comprising, (D) forming an insulating layer on the wiring layer, the insulating layer protecting the wiring layer and preventing oxidation of the wiring layer.

7. The method as set forth in claim 6, wherein the stage (D) includes, disposing a second adhesive on the wiring layer, and disposing an insulating material on the second adhesive layer, followed by pressing.

8. The method as set forth in claim 6, wherein the insulating material is polyimide.

9. The method as set forth in claim 6, wherein the stage (D) includes, coating a solder resist on the wiring layer.

10. The method as set forth in claim 9, wherein the solder resist is a photoresist.

11. The method as set forth in claim 1, wherein the first and second conductive via holes are formed by a mechanical drilling process.

12. The method as set forth in claim 11, wherein the mechanical drilling process is performed by computer numerical control drilling.