Semiconductor wafer carrier

• US 8,820,728 B2
• Filed: 11/13/2009
• Issued: 09/02/2014
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Jao Sheng, Chen, Ming-Fa
• Primary Examiner(s): Wilson, Lee D
• Assistant Examiner(s): BARLOW, ADAM G
• Application Number:
  US12/617,851
• Publication Number:
  US 20100194014A1
• Time in Patent Office: 1,754 Days
• Field of Search: 269/21, 269/289.R, 269/900, 269/903, 298/30, 298/32, 298/52, 292/811
• US Class Current: 269/289.R
• CPC Class Codes: H01L 21/67132 Apparatus for placing on an insulating substrate, e.g. tape
• CPC Class Codes: H01L 21/67346 characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/53961 with work-holder for assembly

Abstract

A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.

Claims

1. A method for protecting semiconductor wafers, the method comprising:

receiving a carrier, the carrier formed by removing a central portion of a material to form a cavity therein;

providing an adhesive within the cavity; and

placing a semiconductor wafer at least partially within the cavity, wherein a portion of the adhesive protects a sidewall of the semiconductor wafer; and

grinding the semiconductor wafer to expose conductive vias within the semiconductor wafer.

2. The method of claim 1, wherein the cavity extends from a top of the carrier between about 200 μ

m and about 300 μ

m.

3. The method of claim 1, wherein the placing a semiconductor wafer displaces the adhesive such that the adhesive and the semiconductor wafer completely fill the cavity.

4. The method of claim 1, wherein the semiconductor wafer at least partially extends away from the cavity.

5. The method of claim 1, wherein the semiconductor wafer further comprises a first side facing the carrier and a second side opposite the first side, wherein the conductive vias extend from the first side towards the second side.

6. The method of claim 1, wherein the adhesive has a thickness of about 100 μ

m.

7. The method of claim 1, wherein the adhesive is an ultra-violet glue.

8. A method for protecting semiconductor wafers, the method comprising:

providing a carrier, the carrier comprising;

a first region with a first thickness; and

a second region with a second thickness greater than the first thickness, wherein the providing the carrier further comprises receiving the carrier with the first region attached to the second region; and

attaching a semiconductor wafer to the first region using an adhesive, wherein the attaching the semiconductor wafer displaces at least a portion of the adhesive into a third region between a sidewall of the semiconductor wafer and the second region; and

chemically mechanically polishing the semiconductor wafer after the attaching the semiconductor wafer to the first region, the chemically mechanically polishing forming a through-substrate via in the semiconductor wafer, wherein the chemically mechanically polishing forms a planar surface.

9. The method of claim 8, further comprising displacing the adhesive such that the adhesive and the semiconductor wafer completely fill a cavity formed by the first region and the second region.

10. The method of claim 8, wherein the chemically mechanically polishing exposes conductive vias located within the semiconductor wafer.

11. The method of claim 8, further comprising:

processing a side of the semiconductor wafer facing away from the carrier; and

removing the semiconductor wafer from the carrier after the semiconductor wafer has been processed.

12. The method of claim 8, further comprising irradiating the adhesive with ultra-violet radiation.

13. The method of claim 8, wherein the placing a semiconductor wafer into contact with the adhesive is performed by evenly lowering the semiconductor wafer onto the adhesive.

14. A method of manufacturing semiconductor devices, the method comprising:

receiving a carrier manufactured by etching a central region of a material to form a depression;

placing an adhesive onto the carrier; and

placing a semiconductor wafer into the depression and in contact with the adhesive but not in contact with any part of the carrier; and

exposing conductive vias within the semiconductor wafer with a grinding process after the placing the semiconductor wafer into the depression, wherein the grinding process planarizes a first side of the semiconductor wafer.

15. The method of claim 14, wherein the placing the semiconductor wafer displaces a portion of the adhesive along a sidewall of the depression.

16. The method of claim 15, wherein the placing the semiconductor wafer displaces a portion of the adhesive to completely fill a space between the carrier and the semiconductor wafer.

17. The method of claim 14, further comprising forming the conductive vias at least partway through the semiconductor wafer prior to the placing the semiconductor wafer into the depression.

18. The method of claim 14, further comprising irradiating the adhesive with ultra-violet radiation.

19. The method of claim 14, wherein the semiconductor wafer extends above a top surface of the carrier after the placing the semiconductor wafer into the depression.