Titanium nitride as sensing layer for microwell structure

• US 8,821,798 B2
• Filed: 01/19/2012
• Issued: 09/02/2014
• Est. Priority Date: 01/19/2012
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Bustillo, James, Rearick, Todd, Hinz, Wolfgang, Fife, Keith
• Primary Examiner(s): Warden, Jill
• Assistant Examiner(s): Handy, Dwayne K
• Application Number:
  US13/354,072
• Publication Number:
  US 20130190211A1
• Time in Patent Office: 957 Days
• Field of Search: 422/82.01, 422/82.02, 422/82.03, 422/83, 422/98, 204/400, 204/403, 204/408, 204/411, 204/412, 204/415, 204/416, 204/192.22, 204/192.23, 204/192.25
• US Class Current: 422/98
• CPC Class Codes: B01L 2200/0668 Trapping microscopic beads
• CPC Class Codes: B01L 2300/0636 Integrated biosensor, microarrays
• CPC Class Codes: B01L 2300/0645 Electrodes
• CPC Class Codes: B01L 2300/0819 Microarrays; Biochips
• CPC Class Codes: B01L 2300/0877 Flow chambers
• CPC Class Codes: B01L 2300/0893 having a very large number of wells, microfabricated wells
• CPC Class Codes: B01L 3/5027 by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip B01L3/5023 takes precedence; micromixers B01F33/30; microreactors for synthesis B01J19/0093; microcapillary devices in general B81B1/00
• CPC Class Codes: B01L 3/502707 characterised by the manufacture of the container or its components by shaping or joining plastic parts B29C59/00, B29C65/00; by laminating B32B37/00; manufacture of microstructural devices in general B81C
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors

Abstract

A method of fabricating a microwell in an array structure is disclosed herein. The array structure can include a plurality of field effect transistors (FETs), where each FET has a gate structure. The method can include disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to the gate structure of at least one FET. A insulation layer can also be disposed on the array structure, where the insulation layer lies above the TiN layer. Further, an opening above the gate structure of the at least one FET can be etched to remove the insulation layer above the gate structure and to expose the TiN layer. A microwell with at least one sidewall formed from the insulation layer and with a bottom surface formed from the TiN layer is a result of the etching process.

Claims

1. A method of fabricating a microwell, the method comprising:

disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to a gate structure of at least one field effect transistor (FET) in an array structure, wherein the array structure comprises a plurality of FETs, each of the plurality of FETs having an associated gate structure;

disposing an insulation layer on the array structure, wherein the insulation layer lies above the TiN layer; and

etching an opening above the gate structure of the at least one FET to remove the insulation layer above the gate structure and to expose the TiN layer, wherein the insulation layer forms at least one sidewall and the TiN layer forms a bottom surface of the microwell,

wherein the disposing the TiN layer comprises disposing the TiN layer above a conduction channel formed by a source and a drain of the FET, wherein the gate structure lies above the conduction channel.

2. The method of claim 1, wherein each of the plurality of FETs is an ion-sensitive field effect transistor (ISFET) with a floating gate structure.

3. The method of claim 1, wherein the disposing the TiN layer comprises disposing the TiN layer on a conductive layer coupled to the floating gate structure.

4. A method of fabricating a microwell, the method comprising:

disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to a gate structure of at least one field effect transistor (FET) in an array structure, wherein the array structure comprises a plurality of FETs, each of the plurality of FETs having an associated gate structure;

disposing an insulation layer on the array structure, wherein the insulation layer lies above the TiN layer; and

etching an opening above the gate structure of the at least one FET to remove the insulation layer above the gate structure and to expose the TiN layer, wherein the insulation layer forms at least one sidewall and the TiN layer forms a bottom surface of the microwell, wherein the insulation layer comprises at least one layer of silicon nitride and at least one layer silicon dioxide, and wherein the etching comprises removing the layers of silicon nitride and silicon dioxide above the gate structure to expose the TiN layer.

5. A method of fabricating a microwell, the method comprising:

disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to a gate structure of at least one field effect transistor (FET) in an array structure, wherein the array structure comprises a plurality of FETs, each of the plurality of FETs having an associated gate structure;

disposing an insulation layer on the array structure, wherein the insulation layer lies above the TiN layer; and

etching an opening above the gate structure of the at least one FET to remove the insulation layer above the gate structure and to expose the TiN layer, wherein the insulation layer forms at least one sidewall and the TiN layer forms a bottom surface of the microwell, wherein the etching the opening above the gate structure comprises etching the opening with a plasma etch, wherein a power level of the plasma etch is adjusted during the etching of the insulation layer.

6. The method of claim 5, wherein the insulation layer comprises a top layer of silicon nitride and a bottom layer of silicon dioxide, and wherein the etching the opening with the plasma etch comprises lowering the power level of the plasma etch after the top layer of silicon nitride is etched.

7. The method of claim 6, wherein the lowering the power level of the plasma etch comprises monitoring a spectral frequency of the plasma etch between the top layer of silicon nitride and the bottom layer of silicon dioxide, and between the bottom layer of silicon dioxide and the TiN layer.

8. A method of fabricating a microwell, the method comprising:

disposing a titanium nitride (TiN) layer on at least one conductive layer coupled to a gate structure of at least one field effect transistor (FET) in an array structure, wherein the array structure comprises a plurality of FETs, each of the plurality of FETs having an associated gate structure;

disposing an insulation layer on the array structure, wherein the insulation layer lies above the TiN layer;

disposing an oxide layer on the insulation layer, wherein the oxide layer lies above the insulation layer and the TiN layer; and

etching an opening above the gate structure of the at least one FET to remove the insulation and oxide layers above the gate structure and to expose the TiN layer, wherein the insulation and oxide layers form at least one sidewall and the TiN layer forms a bottom surface of the microwell.

9. The method of claim 8, wherein each of the plurality of FETs is an ion-sensitive field effect transistor (ISFET) with a floating gate structure, and wherein the disposing the TiN layer comprises disposing the TiN layer on a conductive layer coupled to the floating gate structure.

10. The method of claim 8, wherein the disposing the TiN layer comprises disposing the TiN layer above a conduction channel formed by a source and a drain of the FET, wherein the gate structure lies above the conduction channel.

11. The method of claim 8, wherein the etching the opening above the gate structure comprises removing the insulation and oxide layers above the gate structure to expose the TiN layer.

12. A sensor array comprising:

a plurality of field effect transistors (FETs), wherein at least one FET comprises a gate structure with a conductive layer disposed thereon; and

a plurality of microwells coupled to the plurality of FETs, wherein at least one microwell comprises at least one sidewall formed from at least one of insulation layer and an oxide layer and a bottom surface formed from a titanium nitride (TiN) layer, the TiN layer coupled to the conductive layer, wherein the insulation layer comprises at least one layer of silicon nitride and at least one layer of silicon dioxide and lies above the TiN layer.

13. The sensor array of claim 12, wherein an opening of the at least one microwell is formed by removing the layers of silicon nitride and silicon dioxide above the gate structure to expose the TiN layer.

14. The sensor array of claim 12, wherein the oxide layer lies above the insulation layer and the TiN layer.

15. The sensor array of claim 14, wherein an opening of the at least one microwell is formed by removing the insulation and oxide layers above the gate structure to expose the TiN layer.

16. The sensor array of claim 12, wherein the at least one FET is an ion-sensitive field effect transistor (ISFET) with a floating gate structure.

17. The sensor array of claim 16, wherein the TiN layer is in contact with a conductive layer coupled to the floating gate structure.

18. A sensor array comprising:

a plurality of field effect transistors (FETs), wherein at least one FET comprises a gate structure with a conductive layer disposed thereon; and

a plurality of microwells coupled to the plurality of FETs, wherein at least one microwell comprises at least one sidewall formed from at least one of insulation layer and an oxide layer and a bottom surface formed from a titanium nitride (TiN) layer, the TiN layer coupled to the conductive layer, wherein the TiN layer is above a conduction channel formed by a source and a drain of the FET, wherein the gate structure lies above the conduction channel.