Internal electrical contact for enclosed MEMS devices

• US 8,822,252 B2
• Filed: 09/20/2013
• Issued: 09/02/2014
• Est. Priority Date: 01/30/2013
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Huang, Kegang, Shin, Jongwoo, Lim, Martin, Daneman, Michael Julian, Seeger, Joseph
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US14/033,366
• Publication Number:
  US 20140213007A1
• Time in Patent Office: 347 Days
• Field of Search: 438/51
• US Class Current: 438/51
• CPC Class Codes: B81B 2207/098 Arrangements not provided for in groups B81B2207/092 - B81B2207/097
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: B81C 2203/031 Anodic bondings

Abstract

A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

Claims

1. A method of fabricating electrical connections in an integrated MEMS device comprising:

forming a MEMS wafer comprising;

forming one or more cavities in a first semiconductor layer;

bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer;

etching at least one via through the second semiconductor layer and the dielectric layer;

depositing a conductive material on the second semiconductor layer and filling the at least one via;

patterning and etching the conductive material to form at least one standoff;

depositing a germanium layer on the conductive material;

patterning and etching the germanium layer;

patterning and etching the second semiconductor layer to define one or more MEMS structures; and

bonding the MEMS wafer to a base substrate using a eutectic bond between the germanium layer on the one or more standoffs and aluminum pads of the base substrate.

2. The method of claim 1, wherein the bonding the first semiconductor layer to the second semiconductor layer is a fusion bond.

3. The method of claim 1, wherein etching the at least one via further comprises partially etching into the first semiconductor layer.

4. The method of claim 1, wherein forming the one or more standoffs includes partially etching into the second semiconductor layer.

5. A method of fabricating electrical connections in an integrated MEMS device comprising:

forming a MEMS wafer comprising;

forming one or more cavities in a first semiconductor layer;

bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer;

etching at least one via through the second semiconductor layer and the dielectric layer;

depositing and a conductive material on the second semiconductor layer and filling the at least one via;

selectively removing the conductive layer to expose a portion of the second semiconductor layer;

patterning and etching the second semiconductor layer to form one or more standoffs;

depositing a germanium layer on the second semiconductor layer;

patterning and etching the germanium layer;

patterning and etching the second semiconductor layer to define one or more MEMS structures; and

bonding the MEMS wafer to a base substrate using a eutectic bond between the germanium layer on the one or more standoffs and aluminum pads of the base substrate.

6. The method of claim 5, where the one or more standoffs are formed prior to the depositing and patterning the germanium layer.

7. The method of claim 5, where the one or more standoffs are formed after the depositing and patterning the germanium layer.

8. A method of fabricating electrical connections in an integrated MEMS device comprising:

forming a MEMS wafer comprising;

depositing a dielectric layer on a first semiconductor layer;

patterning and etching at least one via on the dielectric layer;

depositing a second semiconductor layer on the patterned dielectric layer;

depositing a germanium layer on the second semiconductor layer;

patterning and etching the germanium layer and the second semiconductor layer to form one or more standoffs;

patterning and etching the second semiconductor layer to form MEMS structures;

etching the dielectric layer to release the MEMS device structures; and

bonding the MEMS wafer to a base substrate using a eutectic bond between the germanium layer on the one or more standoffs and aluminum pads of the base substrate.

9. The method of claim 8, wherein the deposited second semiconductor layer is comprised of silicon.

10. The method of claim 8, further comprising planarizing the deposited second semiconductor layer.

11. The method of claim 8, where the one or more stand-offs are formed prior to patterning the germanium layer.

12. The method of claim 8, wherein the etching the dielectric layer comprises a vapor etch.

13. The method of claim 8, wherein the etching the dielectric layer comprises a wet etch.