Performance enhancement in transistors by reducing the recessing of active regions and removing spacers

• US 8,822,298 B2
• Filed: 03/15/2012
• Issued: 09/02/2014
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Flachowsky, Stefan, Hoentschel, Jan
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Oh, Jaehwan
• Application Number:
  US13/421,242
• Publication Number:
  US 20120235215A1
• Time in Patent Office: 901 Days
• Field of Search: 438/299, 438/303
• US Class Current: 438/303
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a protective liner above an active region and a gate electrode structure formed on said active region, said gate electrode comprising a dielectric cap layer, wherein the protective liner is formed on and in contact with the gate electrode structure and on and in contact with an upper surface of the dielectric cap layer;

performing a first ion implantation process to form drain and source extension regions in said active region in the presence of said protective liner;

forming a spacer structure on and in contact with said protective liner;

removing an exposed portion of said protective liner by using said spacer structure as an etch mask so as to thereby expose the upper surface of the dielectric cap layer and portions of the active region; and

performing a second ion implantation process to form drain and source regions by forming deep drain and source areas in said exposed portions of the active region in the presence of said spacer structure.

2. The method of claim 1, further comprising performing a common etching process to remove the spacer structure and said dielectric cap layer, wherein a non-removed portion of said protective liner acts as an etch stop material during the common etching process.

3. The method of claim 2, further comprising forming a metal silicide in said gate electrode structure and said drain and source regions.

4. The method of claim 1, further comprising forming a strain-inducing dielectric material above said drain and source regions and above said gate electrode structure.

5. The method of claim 1, further comprising performing a third implantation process so as to introduce a counter doping species in the presence of said protective liner.

6. The method of claim 1, wherein forming said spacer structure comprises depositing a silicon oxide material and patterning said silicon oxide material so as to form a spacer element.

7. The method of claim 6, further comprising forming said dielectric cap layer from a silicon oxide material.

8. The method of claim 1, further comprising forming said gate electrode structure with a gate length of 40 nm or less.

9. A method, comprising:

forming a protective liner above an active region of a transistor, said protective liner covering a gate electrode structure formed on said active region, said gate electrode comprising a dielectric cap layer, wherein the protective liner is formed on and in contact with the gate electrode structure and on and in contact with an upper surface of the dielectric cap layer;

performing a first ion implantation process to form drain and source extension regions by incorporating a drain and source dopant species in said active region through said protective liner;

forming a spacer element on and in contact with said protective liner;

removing an exposed portion of said protective liner by using said spacer structure as an etch mask so as to thereby expose the upper surface of the dielectric cap layer and portions of the active region; and

performing a second ion implantation process to form drain and source regions in said exposed portions of said active region by using said spacer element as an implantation mask; and

performing a common etch process to remove said spacer element and said dielectric cap layer of said gate electrode structure after forming said drain and source regions.

10. The method of claim 9, wherein a non-removed portion of said protective liner acts as an etch stop material during the common etching process.

11. The method of claim 9, wherein performing said common etch process further comprises preparing exposed surface areas of said drain and source regions for forming a metal silicide therein.

12. The method of claim 9, wherein forming said spacer element comprises depositing a silicon oxide material on said protective liner and patterning said silicon oxide material by using said protective liner as an etch stop layer.

13. The method of claim 9, further comprising forming said gate electrode structure so as to include a high-k dielectric material.

14. The method of claim 9, further comprising patterning said protective liner by using said spacer element as an etch mask.

15. The method of claim 14, wherein said protective liner is patterned prior to forming said drain and source regions.

16. The method of claim 14, wherein said protective liner is patterned after forming said drain and source regions.

17. The method of claim 9, further comprising forming a strain-inducing dielectric layer above said active region and said gate electrode structure after removing said spacer element.