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Semiconductor memory device having three-dimensionally arranged resistive memory cells

  • US 8,822,971 B2
  • Filed: 09/07/2012
  • Issued: 09/02/2014
  • Est. Priority Date: 11/25/2011
  • Status: Active Grant
First Claim
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1. A three-dimensional semiconductor device, comprising:

  • a substrate including first and second doped regions separated by a channel region;

    a bit line coupled to the first doped region;

    a vertical electrode coupled to the second doped region;

    a stack of horizontal electrodes between the substrate and the bit line,the stack including mold layers between the horizontal electrodes in a vertical direction,a space between the mold layers and the vertical electrode being greater than a space between the horizontal electrodes and the vertical electrode; and

    a selection line between the substrate and the stack of horizontal electrodes,the selection line has a planar shape and a planar position that is substantially the same as a planar shape and a planar position of the horizontal electrodes.

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