Semiconductor memory device having three-dimensionally arranged resistive memory cells
First Claim
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1. A three-dimensional semiconductor device, comprising:
- a substrate including first and second doped regions separated by a channel region;
a bit line coupled to the first doped region;
a vertical electrode coupled to the second doped region;
a stack of horizontal electrodes between the substrate and the bit line,the stack including mold layers between the horizontal electrodes in a vertical direction,a space between the mold layers and the vertical electrode being greater than a space between the horizontal electrodes and the vertical electrode; and
a selection line between the substrate and the stack of horizontal electrodes,the selection line has a planar shape and a planar position that is substantially the same as a planar shape and a planar position of the horizontal electrodes.
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Abstract
Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.
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Citations
23 Claims
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1. A three-dimensional semiconductor device, comprising:
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a substrate including first and second doped regions separated by a channel region; a bit line coupled to the first doped region; a vertical electrode coupled to the second doped region; a stack of horizontal electrodes between the substrate and the bit line, the stack including mold layers between the horizontal electrodes in a vertical direction, a space between the mold layers and the vertical electrode being greater than a space between the horizontal electrodes and the vertical electrode; and a selection line between the substrate and the stack of horizontal electrodes, the selection line has a planar shape and a planar position that is substantially the same as a planar shape and a planar position of the horizontal electrodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 22)
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10. A three-dimensional semiconductor device, comprising:
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a selection line group including first and second selection lines connected to each other; a plurality of word lines sequentially stacked on each of the first and second selection lines, the plurality of word lines each having a shape that is identical to a shape of at least one of the first and second selection lines; vertical electrodes arranged in a row between the first and second selection lines; mold layers between the word lines in a vertical direction, a space between the mold layers and the vertical electrodes being greater than a space between at least one of the plurality of word lines and the vertical electrodes; a plurality of bit line plugs arranged in a row at each of both sides of the selection line group; and bit lines crossing the word lines and connecting the bit line plugs with each other. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23)
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Specification