Semiconductor memory device having three-dimensionally arranged resistive memory cells

• US 8,822,971 B2
• Filed: 09/07/2012
• Issued: 09/02/2014
• Est. Priority Date: 11/25/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jintaek, Park, Youngwoo, Choi, Jungdal
• Primary Examiner(s): Campbell, Shaun
• Assistant Examiner(s): Vuong, Thai T
• Application Number:
  US13/606,789
• Publication Number:
  US 20130134377A1
• Time in Patent Office: 725 Days
• Field of Search: 257/4
• US Class Current: 257/4
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Claims

1. A three-dimensional semiconductor device, comprising:

a substrate including first and second doped regions separated by a channel region;

a bit line coupled to the first doped region;

a vertical electrode coupled to the second doped region;

a stack of horizontal electrodes between the substrate and the bit line,

the stack including mold layers between the horizontal electrodes in a vertical direction,

a space between the mold layers and the vertical electrode being greater than a space between the horizontal electrodes and the vertical electrode; and

a selection line between the substrate and the stack of horizontal electrodes,

the selection line has a planar shape and a planar position that is substantially the same as a planar shape and a planar position of the horizontal electrodes.

2. The device of claim 1, wherein a horizontal distance between the selection line and the vertical electrode is substantially equivalent to a horizontal distance between the horizontal electrodes and the vertical electrode.

3. The device of claim 1, further comprising:

a bit line plug connecting the bit line with the first doped region,

wherein a horizontal distance between the selection line and the bit line plug is substantially equivalent to a horizontal distance between the horizontal electrodes and the bit line plug.

4. The device of claim 1, wherein

the bit line crosses the horizontal electrodes, and

the selection line and the stack cross the channel region.

5. The device of claim 1, wherein

the selection line overlaps a first portion of the first doped region,

the selection line overlaps a first part of the second doped region, and

a width of the first portion of the first doped region is different than a width of the first part of the second doped region.

6. The device of claim 1, wherein a material of the selection line is substantially the same as a material of the horizontal electrodes.

7. The device of claim 1, further comprising:

memory patterns between the horizontal electrodes and the vertical electrode, wherein

a first horizontal thickness of the memory pattern at a level of at least one of the horizontal electrodes is smaller than a second horizontal thickness of the memory pattern at a level of the mold layer.

8. The device of claim 1, wherein the stack further comprises:

a rectifying element between the horizontal electrodes and the vertical electrode,

wherein a space between the mold layer and the vertical electrode is different from a space between the rectifying element and the vertical electrode.

9. The device of claim 1, further comprising:

memory patterns between the horizontal electrodes and the vertical electrode,

wherein the memory patterns contain at least one of chalcogenides, layered structures configured to exhibit a magnetoresistance property, perovskite compounds, and transition metal oxides.

22. The device of claim 1, further comprising:

memory patterns including parts horizontally between the horizontal electrodes and the vertical electrode,

the memory patterns including other parts horizontally between the selection line and the vertical electrode.

10. A three-dimensional semiconductor device, comprising:

a selection line group including first and second selection lines connected to each other;

a plurality of word lines sequentially stacked on each of the first and second selection lines,

the plurality of word lines each having a shape that is identical to a shape of at least one of the first and second selection lines;

vertical electrodes arranged in a row between the first and second selection lines;

mold layers between the word lines in a vertical direction, a space between the mold layers and the vertical electrodes being greater than a space between at least one of the plurality of word lines and the vertical electrodes;

a plurality of bit line plugs arranged in a row at each of both sides of the selection line group; and

bit lines crossing the word lines and connecting the bit line plugs with each other.

11. The device of claim 10, wherein the word lines are electrically separated from each other and are thereby configured to have different voltages from each other.

12. The device of claim 10, wherein

the word lines delimit a first trench,

the vertical electrodes are in the first trench,

the word lines delimit second trenches,

the bit line plugs are in the second trench, and

each of the second trenches has a length that is sufficient to cross a plurality of the bit lines.

13. The device of claim 12, wherein the first trench has a length that is sufficient to cross a plurality of the bit lines.

14. The device of claim 10, wherein each of the first and second selection lines has a planar shape and a planar position that is substantially the same as a planar shape and a planar position of the plurality of word lines on the first and second selection lines.

15. The device of claim 10, wherein horizontal distances between the first and second selection lines and the vertical electrode are substantially equivalent to horizontal distances between the plurality of word lines and the vertical electrode.

16. The device of claim 10, wherein horizontal distances between the first and second selection lines and the bit line plugs are substantially equivalent to horizontal distances between the word lines and the bit line plugs.

17. The device of claim 10, further comprising:

a plurality of active patterns below the selection line group,

wherein each of the active patterns includes,

a pair of drain regions spaced apart from each other,

a source region between the drain regions, and

a pair of channel regions between the drain regions and the source region, and

the vertical electrodes are coupled to the source regions,

the bit line plugs are coupled to the drain regions, and

the first and second selection lines face the pair of channel regions.

18. The device of claim 17, wherein

a width of each one of the drain regions overlaps with one of the first and second selection lines, and

the width of each one of the drain regions that overlaps with one of the first and second selection lines is different from at least one of a first width of the source region that overlaps with the first selection line and a second width of the source region that overlaps with the second selection line.

19. The device of claim 10, wherein a material of the first and second selection lines is substantially the same as a material of the plurality of word lines.

20. The device of claim 10, further comprising:

memory patterns between the word lines and the vertical electrode, wherein

a first horizontal thickness of the memory pattern at a level of at least one of the plurality of word lines is smaller than a second horizontal thickness of the memory pattern at a level of at least one of the mold layers.

21. The device of claim 10, further comprising:

memory patterns between the word lines and the vertical electrode, wherein the memory patterns contain at least one of chalcogenides, layered structures configured to exhibit a magnetoresistance property, perovskite compounds, and transition metal oxides.

23. The device of claim 10, further comprising:

memory patterns including parts horizontally between the plurality of word lines and the vertical electrodes,

the memory patterns including other parts horizontally between the vertical electrodes and the first and second selection lines.