Semiconductor device

• US 8,822,990 B2
• Filed: 01/28/2013
• Issued: 09/02/2014
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Ohara, Hiroki, Sasaki, Toshinari, Noda, Kosei, Kuwabara, Hideaki
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/751,189
• Publication Number:
  US 20130140559A1
• Time in Patent Office: 582 Days
• Field of Search: 257/43, 257/213, 257/214, 257/E27.111, 257/E29.112
• US Class Current: 257/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Claims

1. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer;

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer;

a pixel electrode layer over the inorganic insulating film, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

2. The semiconductor device according to claim 1, further comprising a capacitor portion over a same substrate,

wherein the capacitor portion comprises a capacitor wiring and a capacitor electrode which overlaps with the capacitor wiring,

wherein a dielectric in the capacitor portion is the gate insulating layer, and

wherein the capacitor wiring and the capacitor electrode are in contact with the gate insulating layer.

3. The semiconductor device according to claim 1,

wherein a width in a channel length direction of the gate electrode layer is smaller than a width in a channel length direction of the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

5. The semiconductor device according to claim 1,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

6. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer are formed of a light-transmitting conductive film.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor layer further comprises gallium and zinc.

10. The semiconductor device according to claim 1,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

11. The semiconductor device according to claim 1, wherein the inorganic insulating film further comprises nitrogen.

12. The semiconductor device according to claim 1, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.

7. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide insulating layer over the oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the oxide semiconductor layer comprises a first region which is in contact with the oxide insulating layer, a second region which is in contact with the source electrode layer or the drain electrode layer, and a third region which is in contact with the inorganic insulating film,

wherein in the first region, a channel formation region is a region which overlaps with the gate electrode layer with the gate insulating layer interposed therebetween,

wherein the third region is provided between the channel formation region and the second region,

wherein the source electrode layer and the drain electrode layer are formed of a light-transmitting conductive film,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

8. The semiconductor device according to claim 7,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

13. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises indium.

14. The semiconductor device according to claim 13, wherein the oxide semiconductor layer further comprises gallium and zinc.

15. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer; and

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer; and

an insulating layer comprising a resin over the inorganic insulating film,

a pixel electrode layer over the insulating layer, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

16. The semiconductor device according to claim 15,

wherein a width in a channel length direction of the gate electrode layer is smaller than a width in a channel length direction of the oxide semiconductor layer.

17. The semiconductor device according to claim 15,

wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

18. The semiconductor device according to claim 15,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

19. The semiconductor device according to claim 15, wherein the oxide semiconductor layer further comprises gallium and zinc.

20. The semiconductor device according to claim 15,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

21. The semiconductor device according to claim 15, wherein the inorganic insulating film further comprises nitrogen.

22. The semiconductor device according to claim 15, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.

23. The semiconductor device according to claim 15, wherein the resin is selected from a group consisting of polyimide, acrylic, benzocyclobutene, polyamide, epoxy and a siloxane-based resin.

24. A semiconductor device comprising:

a gate wiring layer over an insulating surface;

a gate insulating layer over the gate wiring layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate wiring layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer; and

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer;

an insulating layer comprising a resin over the inorganic insulating film,

a pixel electrode layer over the insulating layer, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein whole of the oxide semiconductor layer overlaps with the gate wiring layer,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

25. The semiconductor device according to claim 24,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

26. The semiconductor device according to claim 24, wherein the oxide semiconductor layer further comprises gallium and zinc.

27. The semiconductor device according to claim 24,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

28. The semiconductor device according to claim 24, wherein the inorganic insulating film further comprises nitrogen.

29. The semiconductor device according to claim 24, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.

30. The semiconductor device according to claim 24, wherein the resin is selected from a group consisting of polyimide, acrylic, benzocyclobutene, polyamide, epoxy and a siloxane-based resin.

31. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer; and

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer;

a pixel electrode layer over the inorganic insulating film, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein a resistance in the channel formation region is higher than a resistance in a region of the oxide semiconductor layer, the region being in contact with one of the source electrode layer and the drain electrode layer,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

32. The semiconductor device according to claim 31,

wherein a width in a channel length direction of the gate electrode layer is smaller than a width in a channel length direction of the oxide semiconductor layer.

33. The semiconductor device according to claim 31,

wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

34. The semiconductor device according to claim 31,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

35. The semiconductor device according to claim 31, wherein the oxide semiconductor layer further comprises gallium and zinc.

36. The semiconductor device according to claim 31,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

37. The semiconductor device according to claim 31, wherein the inorganic insulating film further comprises nitrogen.

38. The semiconductor device according to claim 31, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.

39. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer; and

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer;

a pixel electrode layer over the inorganic insulating film, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein a concentration of oxygen in the channel formation region is higher than a concentration of oxygen in a region of the oxide semiconductor layer, the region being in contact with one of the source electrode layer and the drain electrode layer,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

40. The semiconductor device according to claim 39,

wherein a width in a channel length direction of the gate electrode layer is smaller than a width in a channel length direction of the oxide semiconductor layer.

41. The semiconductor device according to claim 39,

wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the source electrode layer or the drain electrode layer with the gate insulating layer and the oxide insulating layer interposed therebetween.

42. The semiconductor device according to claim 39,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

43. The semiconductor device according to claim 39, wherein the oxide semiconductor layer further comprises gallium and zinc.

44. The semiconductor device according to claim 39,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

45. The semiconductor device according to claim 39, wherein the inorganic insulating film further comprises nitrogen.

46. The semiconductor device according to claim 39, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.

47. A semiconductor device comprising:

a gate wiring layer over an insulating surface;

a gate insulating layer over the gate wiring layer;

an oxide semiconductor layer comprising indium over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate wiring layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer being in electrical contact with the oxide semiconductor layer through the first contact hole of the oxide insulating layer; and

a drain electrode layer over the oxide insulating layer, the drain electrode layer being in electrical contact with the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

an inorganic insulating film over the source electrode layer and the drain electrode layer;

a pixel electrode layer over the inorganic insulating film, the pixel electrode layer being in electrical contact with one of the source electrode layer and the drain electrode layer; and

a wiring intersection of a gate wiring layer and a source wiring layer,

wherein the source electrode layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein whole of the oxide semiconductor layer overlaps with the gate wiring layer,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the gate wiring layer includes the gate electrode layer, and

wherein the source wiring layer includes the source electrode layer.

48. The semiconductor device according to claim 47,

wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

49. The semiconductor device according to claim 47, wherein the oxide semiconductor layer further comprises gallium and zinc.

50. The semiconductor device according to claim 47,

wherein the first contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer, and

wherein the second contact hole of the oxide insulating layer completely overlaps with the oxide semiconductor layer.

51. The semiconductor device according to claim 47, wherein the inorganic insulating film further comprises nitrogen.

52. The semiconductor device according to claim 47, wherein the gate insulating layer comprises a silicon nitride film and a silicon oxide film over the silicon nitride film.