Transistor and method for manufacturing the transistor

• US 8,822,991 B2
• Filed: 01/31/2013
• Issued: 09/02/2014
• Est. Priority Date: 02/05/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US13/755,317
• Publication Number:
  US 20130146869A1
• Time in Patent Office: 579 Days
• Field of Search: 257/43, 257/49, 257/52, 257/57, 257/59, 257/66, 257/67, 257/288, 257/E27.06, 257/E29.049, 257/E29.05, 257/E29.14, 257/3, 349/42, 349/43, 349/47, 349/139, 349/140
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

Claims

1. A transistor comprising:

a gate electrode;

a gate insulating layer;

a source electrode layer

a drain electrode layer;

a first metal oxide layer electrically connected to the source electrode layer;

a second metal oxide layer electrically connected to the drain electrode layer; and

an oxide semiconductor layer comprising a first region in contact with the first metal oxide layer, a second region in contact with the second metal oxide layer and a third region,

wherein the oxide semiconductor layer and the gate electrode overlap with each other with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode,

wherein each of the first region and the second region comprises a crystal structure, and

wherein the third region comprises an amorphous structure.

2. The semiconductor device according to claim 1, wherein each of the first metal oxide layer and the second metal oxide layer comprises a crystal structure.

3. The semiconductor device according to claim 1,

wherein each of the first metal oxide layer, the second metal oxide layer, and the oxide semiconductor layer comprises zinc, and

wherein a composition of the first metal oxide layer and the second metal oxide layer is different from a composition of the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein each of the first metal oxide layer and the second metal oxide layer comprises zinc oxide, and

wherein the oxide semiconductor layer comprises indium, zinc, and gallium.

5. The semiconductor device according to claim 1, wherein the first region and the second region comprise more zinc than the third region.

6. The semiconductor device according to claim 1,

wherein the gate electrode is over a substrate,

wherein the gate insulating layer is over the gate electrode,

wherein the source electrode layer and the drain electrode layer are over the gate insulating layer,

wherein the first metal oxide layer is over the source electrode layer,

wherein the second metal oxide layer is over the drain electrode layer, and

wherein the oxide semiconductor layer is on the first metal oxide layer and the second metal oxide layer.

7. The semiconductor device according to claim 1,

wherein the gate electrode is over a substrate,

wherein the gate insulating layer is over the gate electrode,

wherein the oxide semiconductor layer is over the gate insulating layer,

wherein the first metal oxide layer and the second metal oxide layer are on the oxide semiconductor layer,

wherein the source electrode layer is over the first metal oxide layer, and

wherein the drain electrode layer is over the second metal oxide layer.

8. The semiconductor device according to claim 1,

wherein the source electrode layer and the drain electrode layer are over a substrate,

wherein the first metal oxide layer is over the source electrode layer,

wherein the second metal oxide layer is over the drain electrode layer,

wherein the oxide semiconductor layer is on the first metal oxide layer and the second metal oxide layer,

wherein the gate insulating layer is over the oxide semiconductor layer, and

wherein the gate electrode is over the gate insulating layer.

9. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a first oxide layer over the gate electrode with the gate insulating layer between the first oxide layer and the gate electrode, the first oxide layer comprising a first region and a second region over the first region;

a second oxide layer over the second region of the first oxide layer; and

an electrode over the second oxide layer,

wherein each of the first oxide layer and the second oxide layer comprises zinc, and

wherein a concentration of zinc comprised in the second region of the first oxide layer is higher than a concentration of zinc comprised in the first region of the first oxide layer.

10. The semiconductor device according to claim 9,

wherein the first oxide layer is an oxide semiconductor layer, and

wherein the second oxide layer is a metal oxide layer.

11. The semiconductor device according to claim 9,

wherein the first oxide layer further comprises indium.

12. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode, the gate insulating layer comprising silicon;

a first oxide layer over the gate electrode with the gate insulating layer between the first oxide layer and the gate electrode, the first oxide layer comprising an amorphous structure;

a second oxide layer over the first oxide layer, the second oxide layer comprising a crystal structure; and

an electrode over the second oxide layer,

wherein each of the first oxide layer and the second oxide layer comprises zinc, and

wherein the first oxide layer comprises silicon.

13. The semiconductor device according to claim 12,

wherein the first oxide layer is an oxide semiconductor layer, and

wherein the second oxide layer is a metal oxide layer.

14. The semiconductor device according to claim 12,

wherein the first oxide layer further comprises indium.

15. The semiconductor device according to claim 12,

wherein the first oxide layer comprises a first region and a second region over the first region,

wherein each of the first oxide layer and the second oxide layer comprises zinc, and

wherein a concentration of zinc comprised in the second region of the first oxide layer is higher than a concentration of zinc comprised in the first region of the first oxide layer.