Semiconductor element, semiconductor device, and method for manufacturing the same

• US 8,823,074 B2
• Filed: 08/01/2013
• Issued: 09/02/2014
• Est. Priority Date: 12/04/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Kurata, Motomu, Mikami, Mayumi
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/956,444
• Publication Number:
  US 20140027767A1
• Time in Patent Office: 397 Days
• Field of Search: 438/201, 438/211, 438/241, 438/266, 257316-322, 257E29124- 29138
• US Class Current: 257/316
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

The semiconductor element includes an oxide semiconductor layer on an insulating surface; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer. The source electrode layer and the drain electrode layer have sidewalls which are in contact with a top surface of the oxide semiconductor layer.

Claims

1. A semiconductor device comprising a memory circuit, the memory circuit comprising:

a transistor; and

a capacitor,

wherein the transistor comprises;

a semiconductor layer;

a source electrode and a drain electrode over and electrically connected to the semiconductor layer;

a first sidewall over the semiconductor layer, the first sidewall in contact with a side surface of the source electrode;

a second sidewall over the semiconductor layer, the second sidewall in contact with a side surface of the drain electrode;

a first insulating layer over the semiconductor layer, the source electrode, the drain electrode, the first sidewall and the second sidewall; and

a first gate electrode over the first insulating layer, the first gate electrode overlapping with the semiconductor layer,

wherein each of the first sidewall and the second sidewall overlaps with the first gate electrode, and

wherein one of the source electrode and the drain electrode is electrically connected to the capacitor.

2. The semiconductor device according to claim 1, wherein the transistor further comprises:

a second insulating layer under the semiconductor layer; and

a second gate electrode under the second insulating layer, the second gate electrode overlapping with the semiconductor layer.

3. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode overlaps with the first gate electrode.

4. The semiconductor device according to claim 1, wherein each of the first sidewall and the second sidewall comprises an insulating material.

5. The semiconductor device according to claim 1, wherein each of the first sidewall and the second sidewall comprises a conductive material.

6. The semiconductor device according to claim 1, further comprising an antenna operationally connected to the memory circuit.

7. A semiconductor device comprising a memory circuit, the memory circuit comprising:

a transistor; and

a capacitor,

wherein the transistor comprises;

an oxide semiconductor layer;

a source electrode and a drain electrode over and electrically connected to the oxide semiconductor layer;

a first sidewall over the oxide semiconductor layer, the first sidewall in contact with a side surface of the source electrode;

a second sidewall over the oxide semiconductor layer, the second sidewall in contact with a side surface of the drain electrode;

an insulating layer over the oxide semiconductor layer, the source electrode, the drain electrode, the first sidewall and the second sidewall; and

a gate electrode over the insulating layer, the gate electrode overlapping with the oxide semiconductor layer,

wherein each of the first sidewall and the second sidewall overlaps with the gate electrode, and

wherein one of the source electrode and the drain electrode is electrically connected to the capacitor.

8. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

9. The semiconductor device according to claim 7, wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹²/cm³.

10. The semiconductor device according to claim 7, wherein each of the source electrode and the drain electrode overlaps with the gate electrode.

11. The semiconductor device according to claim 7, wherein each of the first sidewall and the second sidewall comprises an insulating material.

12. The semiconductor device according to claim 7, wherein each of the first sidewall and the second sidewall comprises a conductive material.

13. The semiconductor device according to claim 7, further comprising an antenna operationally connected to the memory circuit.

14. A semiconductor device comprising a memory circuit, the memory circuit comprising:

a transistor; and

a capacitor,

wherein the transistor comprises;

a first gate electrode;

a first insulating layer over the first gate electrode;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer overlapping with the first gate electrode;

a source electrode and a drain electrode over and electrically connected to the oxide semiconductor layer;

a first sidewall over the oxide semiconductor layer, the first sidewall in contact with a side surface of the source electrode;

a second sidewall over the oxide semiconductor layer, the second sidewall in contact with a side surface of the drain electrode;

a second insulating layer over the oxide semiconductor layer, the source electrode, the drain electrode, the first sidewall and the second sidewall; and

a second gate electrode over the second insulating layer, the second gate electrode overlapping with the oxide semiconductor layer,

wherein each of the first sidewall and the second sidewall overlaps with the second gate electrode, and

wherein one of the source electrode and the drain electrode is electrically connected to the capacitor.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

16. The semiconductor device according to claim 14, wherein a carrier concentration in the oxide semiconductor layer is lower than 1×

10¹²/cm³.

17. The semiconductor device according to claim 14, wherein each of the source electrode and the drain electrode overlaps with the second gate electrode.

18. The semiconductor device according to claim 14, wherein each of the first sidewall and the second sidewall comprises an insulating material.

19. The semiconductor device according to claim 14, wherein each of the first sidewall and the second sidewall comprises a conductive material.

20. The semiconductor device according to claim 14, further comprising an antenna operationally connected to the memory circuit.

21. The semiconductor device according to claim 14, wherein a fixed potential is supplied to the first gate electrode.