Dense arrays and charge storage devices

• US 8,823,076 B2
• Filed: 03/27/2014
• Issued: 09/02/2014
• Est. Priority Date: 08/14/2000
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Subramanian, Vivek, Cleeves, James M., Kouznetzov, Igor G., Johnson, Mark G., Farmwald, Paul Michael
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US14/227,425
• Publication Number:
  US 20140217491A1
• Time in Patent Office: 159 Days
• Field of Search: 257/314, 257/316, 257/321, 257/324
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A memory device, comprising:

a silicon substrate;

a first vertical channel located over the silicon substrate;

a second vertical channel located horizontally adjacent to the first vertical channel in a first row over the silicon substrate;

a third vertical channel located horizontally adjacent to the first vertical channel in a second row different from the first row over the silicon substrate;

contacts coupling to the first vertical channel;

contacts coupling to the second vertical channel;

contacts coupling to the third vertical channel;

a first charge storage region located adjacent to a first portion of the first vertical channel;

a first control gate located adjacent to the first charge storage region;

a second charge storage region located adjacent to a second portion of the first vertical channel above the first portion of the first vertical channel; and

a second control gate located adjacent to the second charge storage region;

wherein the first charge storage region and the second charge storage region comprise a continuous charge storage dielectric film and a continuous tunneling dielectric located between the first vertical channel and both the first and the second control gates; and

wherein the first control gate is shared between the first vertical channel, the second vertical channel and the third vertical channel; and

driver circuitry associated with the operation of said memory device.

2. The memory device of claim 1, wherein the device comprises a monolithic three dimensional array of charge storage devices comprising a plurality of device levels.

3. The memory device of claim 1, wherein the contacts coupling to the first vertical channel comprise a first contact which couples to a lower portion of the first vertical channel and a second contact which couples to an upper portion of the first vertical channel.

4. The memory device of claim 3, wherein the first and the second control gates are located above the first contact and below the second contact.

5. The memory device of claim 1, wherein the second control gate is located above the first control gate.

6. The memory device of claim 5, further comprising an insulating layer which is located between the first and the second control gates and electrically isolates the first control gate from the second control gate.

7. The memory device of claim 1, wherein the first charge storage region and the second charge storage region further comprise a control gate dielectric located between both the first and the second control gates and the continuous charge storage dielectric film.

8. The memory device of claim 7, wherein the continuous charge storage dielectric film comprises a silicon nitride dielectric film or an insulating layer containing conductive nanocrystals.

9. The memory device of claim 7, wherein:

the continuous tunneling dielectric comprises a first oxide layer;

the continuous charge storage dielectric film comprises a silicon nitride layer; and

the control gate dielectric comprises a second oxide layer;

the first charge storage region comprises a first portion of the first oxide layer located adjacent to a first portion of the first vertical channel, a first portion of the silicon nitride layer located adjacent to the first portion of the first oxide layer, and a first portion of the second oxide layer located adjacent to the first portion of the silicon nitride layer; and

the second charge storage region comprises a second portion of the first oxide layer located adjacent to a second portion of the first vertical channel, a second portion of the silicon nitride layer located adjacent to the second portion of the first oxide layer, and a second portion of the second oxide layer located adjacent to the second portion of the silicon nitride layer; and

the driver circuitry is at least partially in the silicon substrate and below the first and the second vertical channels.

10. The memory device of claim 1, wherein the first vertical channel comprises a first semiconductor containing pillar, the second vertical channel comprises a second semiconductor containing pillar, and the third vertical channel comprises a third semiconductor containing pillar.

11. The memory device of claim 10, wherein the first control gate is located between the first semiconductor containing pillar, the second semiconductor containing pillar and the third semiconductor containing pillar.

12. The memory device of claim 11, wherein:

the memory device further comprises a plurality of horizontally separated vertical channels comprising a plurality of horizontally separated semiconductor containing pillars;

the first control gate is shared between the plurality of horizontally separated semiconductor containing pillars; and

the first control gate is located between the plurality of horizontally separated semiconductor containing pillars.

13. The memory device of claim 12, wherein:

the plurality of horizontally separated vertical channels comprise a three by three array of horizontally separated semiconductor containing pillars;

the first control gate is shared between the three by three array of horizontally separated semiconductor containing pillars; and

the first control gate is located between the horizontally separated semiconductor containing pillars of the three by three array of horizontally separated semiconductor containing pillars.

14. The memory device of claim 12, wherein the plurality of horizontally separated semiconductor containing pillars each have a substantially circular shape when viewed from above.

15. The memory device of claim 10, wherein the first vertical channel comprises a first silicon containing pillar, the second vertical channel comprises a second silicon containing pillar, and the third vertical channel comprises a third silicon containing pillar.

16. A monolithic three dimensional array of charge storage devices comprising a plurality of device levels, comprising:

a silicon substrate;

a plurality of horizontally separated vertical semiconductor containing channels arranged in a plurality of rows;

a first control gate which is shared between at least two of the plurality of horizontally separated vertical semiconductor containing channels located in a first row of the plurality of rows and between at least two of the plurality of horizontally separated vertical semiconductor containing channels located in different rows of the plurality of rows;

a second control gate which is shared between at least two of the plurality of horizontally separated vertical semiconductor containing channels located in the first row and between at least two of the plurality of horizontally separated vertical semiconductor containing channels located in the different rows, wherein the second control gate is located above the first control gate; and

a charge storage region located between a first one of the plurality of horizontally separated semiconductor containing channels and the first and the second control gates; and

driver circuitry associated with the operation of said array of charge storage devices.

17. The monolithic three dimensional array of claim 16, wherein:

the first control gate is located between the plurality of horizontally separated semiconductor containing channels;

the second control gate is located between the plurality of horizontally separated semiconductor containing channels; and

the charge storage region comprises a continuous layer or film located between at least the first one of the plurality of semiconductor containing channels and both the first and the second control gates.

18. The monolithic three dimensional array of claim 17, wherein the charge storage region comprises a silicon nitride dielectric film or an insulating layer containing conductive nanocrystals.

19. The monolithic three dimensional array of claim 17, wherein the charge storage region comprises a first oxide layer located adjacent to a first portion of a first vertical semiconductor containing channel, a nitride located adjacent to the first oxide layer, and a second layer located adjacent to the nitride charge storage layer.

20. The monolithic three dimensional array of claim 19, wherein the tunneling dielectric comprises a continuous tunneling dielectric located between at least the first one of the plurality of semiconductor containing channels and both the first and the second control gates.

21. The monolithic three dimensional array of claim 16, wherein the charge storage region comprises a floating gate.

22. The monolithic three dimensional array of claim 16, wherein each of the plurality of semiconductor containing channels comprises a respective first contact which couples to a lower portion of the semiconductor containing channel and a respective second contact which couples to an upper portion of the semiconductor containing channel.

23. The monolithic three dimensional array of claim 16, further comprising an insulating layer which is located between the first and the second control gates and electrically isolates the first control gate from the second control gate.

24. The monolithic three dimensional array of claim 16, wherein:

the plurality of horizontally separated vertical semiconductor containing channels comprise a three by three array of horizontally separated vertical semiconductor containing channels;

the first control gate is shared between the three by three array of horizontally separated vertical semiconductor containing channels; and

the first control gate is located between the horizontally separated vertical semiconductor containing channels of the three by three array of horizontally separated vertical semiconductor containing channels.

25. The monolithic three dimensional array of claim 16, wherein the plurality of horizontally separated vertical semiconductor containing channels each have a substantially circular shape when viewed from above.

26. The monolithic three dimensional array of claim 19, wherein the plurality of horizontally separated vertical semiconductor containing channels each have a substantially circular shape when viewed from above.