SiC semiconductor power device

• US 8,823,089 B2
• Filed: 04/15/2011
• Issued: 09/02/2014
• Est. Priority Date: 04/15/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Rupp, Roland
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US13/087,780
• Publication Number:
  US 20120261673A1
• Time in Patent Office: 1,236 Days
• Field of Search: 257/331, 257/328, 257/76, 257/77, 257/24, 257/E29.104
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor power device includes a SiC semiconductor body. At least part of the SiC semiconductor body constitutes a drift zone. A first contact is at a first side of the SiC semiconductor body. A second contact is at a second side of the SiC semiconductor body. The first side is opposite the second side. A current path between the first contact and the second contact includes at least one graphene layer.

Claims

1. A vertical semiconductor power device, comprising:

a SiC semiconductor body, at least part of the SiC semiconductor body constituting a drift zone;

a first contact at a first side of the SiC semiconductor body;

a second contact at a second side of the SiC semiconductor body, the first side being opposite the second side;

a current path between the first contact and the second contact which includes at least one graphene layer; and

a plurality of first trenches extending into the SiC semiconductor body from the second side, wherein the at least one graphene layer is arranged on at least part of a sidewall of the plurality of first trenches,

wherein the at least one graphene layer is distinct from a gate-controlled channel-forming region of the vertical semiconductor power device,

wherein the second contact is formed outside and continuously covers the plurality of first trenches.

2. The vertical power semiconductor device of claim 1, wherein the SiC semiconductor body includes a SiC substrate and an epitaxial SiC layer above the SiC substrate.

3. The vertical power semiconductor device of claim 1, wherein the plurality of first trenches include at least one trench extending into a depth of the SiC semiconductor body in a range of 50 μ

m to 150 μ

m, wherein the at least one trench has a width in a range of 50 nm to 500 nm.

4. The vertical power semiconductor device of claim 1, wherein the at least one graphene layer comprises a stack of two or more graphene layers.

5. The vertical power semiconductor device of claim 1, wherein the current path within the drift zone between the first contact and the second contact includes the at least one graphene layer and, connected in parallel, a part of the SiC semiconductor body.

6. The vertical semiconductor power device of claim 1, wherein:

the vertical semiconductor power device is an FET device; and

the first contact is a contact to one of a source and drain of the FET device and the second contact is a contact to the other one of the source and drain.

7. The vertical power semiconductor device of claim 1, further comprising a plurality of second trenches extending into the SiC semiconductor body from the first side, wherein a second one of the at least one graphene layer is arranged on at least part of a sidewall of the plurality of second trenches.

8. The vertical power semiconductor device of claim 7, wherein a conductivity type of the drift zone is one of n-type and p-type.

9. The vertical power semiconductor device of claim 7, further comprising an electrode arranged within the plurality of second trenches, the electrode configured to control a conductivity of the second graphene layer via a voltage applied to the electrode.

10. A vertical semiconductor power device, comprising:

a SiC semiconductor body, at least part of the SiC semiconductor body constituting a drift zone;

a first contact at a first side of the SiC semiconductor body;

a second contact at a second side of the SiC semiconductor body, the first side being opposite the second side;

a plurality of trenches extending into the SiC semiconductor body from the second side; and

at least one graphene layer arranged on at least part of a sidewall of the plurality of trenches,

wherein the at least one graphene layer is distinct from a gate-controlled channel-forming region of the vertical semiconductor power device,

wherein the second contact is formed outside and continuously covers the plurality of first trenches.

11. The vertical power semiconductor device of claim 10, wherein a current path within the drift zone between the first contact and the second contact includes the at least one graphene layer and, connected in parallel, a part of the SiC semiconductor body between the plurality of trenches.

12. The vertical semiconductor power device of claim 10, wherein the first and second contacts are one of a pair of contacts to a source and drain of an FET, of a pair of contacts to a cathode and anode of a diode, or a pair of contacts to an emitter and collector of an IGBT.