High-voltage transistor structure with reduced gate capacitance

• US 8,823,093 B2
• Filed: 06/25/2012
• Issued: 09/02/2014
• Est. Priority Date: 09/29/2009
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Parthasarathy, Vijay
• Primary Examiner(s): GEBREMARIAM, SAMUEL A
• Application Number:
  US13/532,583
• Publication Number:
  US 20120273885A1
• Time in Patent Office: 799 Days
• Field of Search: 257/335, 257/408
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.

Claims

1. A high voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a first well region of a second conductivity type disposed in the substrate, the first well region having a lateral boundary;

a drain region of the second conductivity type disposed in the first well region, the drain region having a first dimension in a first lateral direction, an extended drain region of the first well region separating the drain region from the lateral boundary in a second lateral direction orthogonal to the first lateral direction;

a second well region of the first conductivity type disposed in the substrate, the second well region extending past the lateral boundary into the first well region;

a source region of the second conductivity type disposed in the second well region, a channel region being defined between the source region and the first well region;

a field oxide layer that substantially covers the first well region, the field oxide layer having a first thickness and extending in the second lateral direction from the drain region to near the second well region in an active area of the HVFET, the field oxide layer extending past the lateral boundary to the source region in an inactive area of the HVFET;

a gate oxide that covers the channel region in the active area, the gate oxide having a second thickness substantially thinner than the first thickness;

a gate disposed over the channel region, the gate extending in the second lateral direction from the source region to at least the field oxide layer, the gate being insulated from the channel region by the gate oxide in the active area, the gate being separated from the first and second well regions over the inactive area by at least the first dimension of the field oxide layer.

2. The HVFET of claim 1 wherein the gate oxide has a substantially linear edge that extends in the first lateral direction, the substantially linear edge having a second dimension in the active area.

3. The HVFET of claim 2 wherein the gate extends in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide.

4. The HVFET of claim 2 wherein the second dimension is greater than or equal to the first dimension.

5. The HVFET of claim 2 wherein the second dimension is approximately equal to the first dimension.

6. The HVFET of claim 2 wherein the gate oxide includes first and second outside corner areas respectively located at opposite ends of the substantially linear edge.

7. The HVFET of claim 6 wherein the first and second outside corner areas of the gate oxide each include a transition area between the active area and inactive area, the transition area having a curved shape that extends in the first and second directions.

8. The HVFET of claim 7 wherein the curved shape comprises a semi-circular shape.

9. The HVFET of claim 1 further comprising a buried region of the first conductivity type disposed within the first well region, a first conduction channel being formed above the buried region and a second conduction channel being formed below the buried region, the buried region being spaced-apart from the drain region the first conductivity type is P-type and the second conductivity type is N-type.

10. The HVFET of claim 1 wherein the first dimension comprises a length of a linear portion of the drain region.