Semiconductor and optoelectronic devices

• US 8,823,122 B2
• Filed: 03/16/2012
• Issued: 09/02/2014
• Est. Priority Date: 10/13/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/422,057
• Publication Number:
  US 20130069191A1
• Time in Patent Office: 900 Days
• Field of Search: 257/432, 257/435, 257/440
• US Class Current: 257/432
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14605 Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/34 containing only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystalline layer includes single crystal transistors.

Claims

1. An integrated device, comprising:

a first crystalline layer covered by an oxide layer,

a second crystalline layer overlying said oxide layer,

wherein said first and second crystalline layers are image sensor layers,

and said device comprises a third crystalline layer, wherein

said third crystalline layer comprises single crystal transistors.

2. An integrated device according to claim 1, wherein

at least one of said image sensor layers and said single crystal transistors are aligned to each other.

3. An integrated device according to claim 1, wherein

said first crystalline layer is sensitive to a different spectrum than said second crystalline layer.

4. An integrated device according to claim 1, wherein

said first crystalline layer has at least an order of magnitude difference in light sensitivity than said second crystalline layer.

5. An integrated device according to claim 1, wherein

at least one of said image sensor layers comprises a polarizer.

6. An integrated device according to claim 1, wherein

said single crystal transistors form a plurality of pixel control circuits.

7. An integrated image sensor, comprising:

a first mono-crystal layer to comprise a plurality of image sensor pixels and alignment marks, and

an oxide layer overlaying and on top of said first mono-crystal layer, and

a second mono-crystal layer to comprise a plurality of second image sensor pixels aligned to said alignment marks, and said second mono-crystal layer overlaying said oxide layer, and

a third mono-crystal layer, wherein

said third mono-crystal layer to comprise a plurality of single crystal transistors aligned to said alignment marks.

8. An integrated device according to claim 7, wherein

said third mono-crystal layer is less than 2 microns thick.

9. An integrated device according to claim 7, wherein

said aligned comprises less than 1 micron alignment error.

10. An integrated device according to claim 7, wherein

said first mono-crystal layer is sensitive to a different spectrum than said second mono-crystal layer.

11. An integrated device according to claim 7, wherein

said first mono-crystal layer has at least an order of magnitude difference in light sensitivity than said second mono-crystal layer.

12. An integrated device according to claim 7, wherein

at least one of said first mono-crystal and said second mono-crystal layers is less than 2 microns thick.

13. An integrated device according to claim 7, wherein

at least one of said first mono-crystal and said second mono-crystal layers comprise a polarizer.

14. An integrated device according to claim 7, wherein

said single crystal transistors form a plurality of pixel control circuits.

15. An integrated device, comprising:

a first mono-crystal layer to comprise a plurality of single crystal transistors and alignment marks, and

an overlaying oxide on top of said first mono-crystal layer, and

a second mono-crystal layer overlaying said oxide, and

wherein said second mono-crystal layer to comprise a plurality of image sensor pixels aligned to said alignment marks.

16. An integrated device according to claim 15, wherein

said second mono-crystal layer is less than 2 microns thick.

17. An integrated device according to claim 15, wherein

said image sensor pixels and said single crystal transistors are aligned to each other.

18. An integrated device according to claim 15, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

19. An integrated device according to claim 15, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer has at least an order of magnitude difference in light sensitivity than said second image sensor layer.

20. An integrated device according to claim 15, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

at least one of said two crystalline layers is less than 2 microns thick.

21. An integrated device according to claim 15, wherein

said second mono-crystal layer comprises a polarizer.

22. An integrated device according to claim 15, wherein

said single crystal transistors form a plurality of pixel control circuits.