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On chip inductor with frequency dependent inductance

  • US 8,823,136 B2
  • Filed: 02/20/2013
  • Issued: 09/02/2014
  • Est. Priority Date: 03/18/2009
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a first metal line embedded in a dielectric material layer located on a semiconductor substrate and resistively connected to a first device at a first end of said first metal line and resistively connected to a second device at a second end of said first metal line;

    a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

    a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded, wherein said first metal line includes a first sidewall and said second metal line includes a second sidewall, wherein said first and second sidewalls are substantially parallel to each other and abut said portion of said dielectric material layer and laterally separated from each other by a substantially constant spacing.

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