Semiconductor package with interface substrate having interposer

• US 8,823,144 B2
• Filed: 10/11/2013
• Issued: 09/02/2014
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Khan, Rezaur Rahman, Zhao, Sam Ziqun
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/052,466
• Publication Number:
  US 20140035163A1
• Time in Patent Office: 326 Days
• Field of Search: 257/621, 257/686, 257/777, 257/778, 257/E21.597, 257/E23.011, 257/E23.085, 257/E23.174
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/12 Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Claims

1. An interface substrate comprising:

an interposer having a first plurality of through-semiconductor vias (TSVs) for electrically connecting a first plurality of lower interconnect pads to a first plurality of upper interconnect pads;

a lower substrate having an opening, wherein the lower substrate is adjacent to the interposer;

a second plurality of lower interconnect pads for receiving a lower semiconductor die, wherein the second plurality of lower interconnect pads is capable of connection to a second plurality of upper interconnect pads, is within the opening, and is adjacent to the interposer.

2. The interface substrate of claim 1, wherein said interposer comprises silicon.

3. The interface substrate of claim 2, wherein said first plurality of TSVs are through-silicon vias.

4. The interface substrate of claim 1, wherein a pitch of said second plurality of lower interconnect pads is less than a pitch of said first plurality of upper interconnect pads.

5. The interface substrate of claim 1, further comprising a plurality of upper contact pads capable of connection to the first and second pluralities of upper interconnect pads, wherein a pitch of the second plurality of lower interconnect pads is less than a pitch of the plurality of upper contact pads.

6. The interface substrate of claim 1, further comprising an upper substrate having a plurality of upper contact pads, the upper substrate being adjacent to the interposer, wherein the plurality of upper contact pads is capable of receiving an upper semiconductor die and is capable of connection to the first and second pluralities of upper interconnect pads.

7. A semiconductor package comprising:

an interposer having a first plurality of through-semiconductor vias (TSVs) for electrically connecting a first plurality of lower interconnect pads to a first plurality of upper interconnect pads;

a lower substrate having an opening, wherein the lower substrate is adjacent to the interposer;

a second plurality of lower interconnect pads for receiving a lower semiconductor die, wherein the second plurality of lower interconnect pads is capable of connection to a second plurality of upper interconnect pads, is within the opening, and is adjacent to the interposer;

a plurality of upper contact pads capable of connection to the first and second pluralities of upper interconnect pads, the plurality of upper contact pads for receiving an upper semiconductor die.

8. The semiconductor package of claim 7, wherein said interposer comprises silicon.

9. The semiconductor package of claim 8, wherein said first plurality of TSVs are through-silicon vias.

10. The semiconductor package of claim 7, wherein a pitch of said second plurality of lower interconnect pads is less than a pitch of said first plurality of upper interconnect pads.

11. The semiconductor package of claim 7, wherein a pitch of the second plurality of lower interconnect pads is less than a pitch of the plurality of upper contact pads.

12. The semiconductor package of claim 7, wherein said upper semiconductor die is a flip-chip.

13. The semiconductor package of claim 7, wherein said lower semiconductor die is a flip-chip.

14. The semiconductor package of claim 7, further comprising an upper substrate adjacent to the interposer, wherein the upper substrate comprises the plurality of upper contact pads, the first plurality of upper interconnect pads, and the second plurality of upper interconnect pads.