Semiconductor device packages having stacking functionality and including interposer

• US 8,823,156 B2
• Filed: 02/09/2011
• Issued: 09/02/2014
• Est. Priority Date: 02/10/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Hsieh, Po-Chi
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US13/024,270
• Publication Number:
  US 20110193205A1
• Time in Patent Office: 1,301 Days
• Field of Search: None
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.

Claims

1. A semiconductor device package, comprising:

a substrate including a first surface, a second surface opposite the first surface, a plurality of first electrical contacts disposed on or adjacent to the first surface, and a plurality of second electrical contacts disposed on or adjacent to the second surface;

a semiconductor chip disposed on or adjacent to the second surface of the substrate, and electrically coupled to the substrate; and

an interposer disposed on or adjacent to the semiconductor chip and electrically coupled to the substrate;

wherein at least one of the first contacts is electrically coupled to at least one of the second contacts through the interposer.

2. The semiconductor device package of claim 1, wherein the substrate further includes a conductive via extending through the substrate, and the at least one of the first contacts is electrically coupled to the at least one of the second contacts through the interposer and the conductive via.

3. The semiconductor device package of claim 1 wherein the first contacts include a plurality of wire bond pads, the wire bond pads being laterally spaced from the chip, the interposer being electrically coupled to a first subset of the wire bond pads by wire bonding, and the chip being electrically coupled to a second subset of the wire bond pads by wire bonding.

4. The semiconductor device package of claim 3, wherein the first contacts further include a plurality of solder pads that are laterally spaced from the chip, with the wire bond pads being disposed between the solder pads and the chip.

5. The semiconductor device package of claim 1, further comprising a package body covering at least the chip and the interposer.

6. The semiconductor device package of claim 5, wherein the package body stops short of at least one edge of the substrate, leaving a subset of the electrical contacts exposed.

7. The semiconductor device package of claim 5, wherein the package body extends to edges of the substrate, but leaves a subset of the electrical contacts exposed.

8. The semiconductor device package of claim 7, wherein the package body defines a plurality of cavities that leave the subset of the electrical contacts exposed.

9. The semiconductor device package of claim 7, wherein the package body includes a center portion and a peripheral portion surrounding the center portion, the peripheral portion having a lesser height than the center portion, and the peripheral portion exposes the subset of the electrical contacts.

10. The semiconductor device package of claim 1, wherein the interposer includes:

a dielectric base layer;

a first interposer pad disposed on or adjacent to the base layer and electrically coupled to the at least one of the first contacts;

a second interposer pad disposed on or adjacent to the base layer and electrically coupled to the at least one of the second contacts; and

a conductive trace disposed on or adjacent to the base layer and electrically coupled between the first interposer pad and the second interposer pad.

11. The semiconductor device package of claim 10, wherein the first interposer pad is disposed adjacent a first edge of the interposer, and the second interposer pad is disposed adjacent a second edge of the interposer.

12. A semiconductor device package, comprising:

a substrate including an upper surface, a plurality of electrical contacts disposed on or adjacent to the upper surface;

a chip coupled to the upper surface of the substrate, and electrically coupled to the substrate, the chip including a plurality of edges; and

an interposer disposed on or adjacent to the chip and electrically coupled to the substrate;

wherein a first one of the contacts is located adjacent a first one of the edges of the chip, and a second one of the contacts is located adjacent a second one of the edges of the chip, and the first contact is electrically coupled to the second contact through the interposer.

13. The semiconductor device package of claim 12, wherein the interposer includes:

a dielectric base layer;

a first interposer pad disposed on or adjacent to the base layer and electrically coupled to the at least one of the first contacts;

a second interposer pad disposed on or adjacent to the base layer and electrically coupled to the at least one of the second contacts; and

a conductive trace disposed on or adjacent to the base layer and electrically coupled between the first interposer pad and the second interposer pad.

14. The semiconductor device package of claim 13, wherein the first interposer pad is disposed adjacent a first edge of the interposer, and the second interposer pad is disposed adjacent a second edge of the interposer.

15. The semiconductor device package of claim 12, wherein the first contacts include a plurality of wire bond pads, the wire bond pads being laterally spaced from the chip, the interposer being electrically coupled to a first subset of the wire bond pads by wire bonding, and the chip being electrically coupled to a second subset of the wire bond pads by wire bonding.

16. The semiconductor device package of claim 15, wherein the first contacts further include a plurality of solder pads that are laterally spaced from the chip, with the wire bond pads being disposed between the solder pads and the chip.