Stacked microelectronic devices

• US 8,823,159 B2
• Filed: 07/02/2013
• Issued: 09/02/2014
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ye, Seng Kim Dalson, Chong, Chin Hui, Lee, Choon Kuan, Lee, Wang Lai, Said, Roslan Bin
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US13/933,607
• Publication Number:
  US 20130292853A1
• Time in Patent Office: 427 Days
• Field of Search: None
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Claims

1. A stacked microelectronic device, comprising:

a first interposer substrate having a first side and a second side facing away from the first side;

a first microelectronic die attached to the first side of the first interposer substrate;

a second interposer substrate having a first side facing away from the first microelectronic die and a second side facing the first microelectronic die, wherein the first microelectronic die is positioned between the first and second interposer substrates, wherein the first interposer substrate is electrically coupled to the first microelectronic die and to the second interposer substrate;

a wire-bond connecting a periphery of the microelectronic die and the first interposer substrate;

a third interposer substrate having a first side and a second side facing away from the first side, the second side facing the second interposer substrate;

a second microelectronic die attached to the first side of the third interposer substrate;

a fourth interposer substrate attached to the second microelectronic die, wherein the second microelectronic die is positioned between the third and fourth interposer substrates, wherein the third interposer substrate is electrically coupled to the second microelectronic die and the fourth interposer substrate; and

an electrical coupling between the second and third interposer substrates.

2. The device of claim 1 wherein an active side of the first microelectronic die faces away from the first interposer substrate.

3. The device of claim 1 wherein an active side of the second microelectronic die faces the third interposer substrate.

4. The device of claim 1 wherein the electrical coupling between the second and third interposer substrates comprises an array of solderballs.

5. The device of claim 4 wherein the fourth interposer substrate has a first side facing away from the second microelectronic die and a second side opposite from the first side, further comprising an encapsulation around a perimeter portion of the first side of the fourth interposer substrate, wherein the encapsulation leaves exposed a central region of the first side of the fourth interposer substrate.

6. The device of claim 5, further comprising an encapsulation around a perimeter portion of the first side of the second interposer substrate, wherein the encapsulation leaves exposed a central region of the first side of the second interposer substrate.

7. The device of claim 1, further comprising an array of solderballs connecting an active side of the first microelectronic device and the second interposer substrate.

8. The device of claim 1, further comprising:

a first set of wirebonds positioned for electrically connecting the first interposer substrate and the first microelectronic die; and

a second set of wirebonds positioned for electrically connecting the first interposer substrate and the second interposer substrate.

9. The device of claim 8, further comprising:

a third set of wirebonds positioned for electrically connecting the third interposer substrate and the second microelectronic die; and

a fourth set of wirebonds positioned for electrically connecting the third interposer substrate and the fourth interposer substrate.

10. The device of claim 1 wherein the first microelectronic die includes an array of bond-pads on an active side of the first microelectronic die, and wherein the second interposer substrate is positioned within an outline of the array of the bond-pads on the active side of the first microelectronic die.

11. A microelectronic device, comprising:

a plurality of microelectronic dies mounted to a first interposer substrate;

a plurality of second interposer substrates corresponding to the plurality of microelectronic dies, the second interposer substrates each having a first side and a second side, wherein the microelectronic dies are positioned between the first interposer substrate and the second side of the corresponding second interposer substrates;

first electrical couplers connecting the first side of the second interposer substrates and the first interposer substrate; and

an encapsulation around a perimeter portion of the first sides of the second interposer substrates, wherein the encapsulation leaves a central region of the first sides of the second interposer substrates exposed.

12. The device of claim 11, further comprising second electrical couplers directly connecting an active side of at least one microelectronic die with the first interposer substrate.

13. The device of claim 12 wherein the second electrical couplers are wirebonds.

14. The device of claim 13 wherein the wirebonds are routed through one or more openings in the first interposer substrate.

15. The device of claim 14 wherein the encapsulation is the first encapsulation, the device further comprising a second encapsulation encapsulating the wirebonds at one or more openings in the first interposer substrate.

16. The device of claim 12 wherein the second electrical couplers are solderballs.

17. The device of claim 11, further comprising second electrical couplers directly connecting an active side of at least one microelectronic die with the second interposer substrate.

18. The device of claim 11 wherein active sides of the microelectronic dies face the first interposer substrate.

19. The device of claim 11 wherein the first interposer substrate has a first side facing the microelectronic dies and a second side facing away from the microelectronic dies, the device further comprising a plurality of solderballs at the second side of the first interposer substrate.