Bandgap ready circuit

• US 8,823,267 B2
• Filed: 06/06/2012
• Issued: 09/02/2014
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ochoa, Agustin
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US13/490,236
• Publication Number:
  US 20120313665A1
• Time in Patent Office: 818 Days
• Field of Search: None
• US Class Current: 315/104
• CPC Class Codes: G05F 1/613 using semiconductor devices in parallel with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G06K 19/0715 the arrangement including means to regulate power transfer to the integrated circuit
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Claims

1. A bandgap ready circuit comprising:

a bandgap circuit for providing a bandgap voltage;

a first replica branch and a second replica branch;

a first comparator for monitoring a first voltage in the first replica branch and a second voltage at a first node in the bandgap circuit and for providing a first logic signal;

a second comparator for monitoring a third voltage in the second replica branch and a fourth voltage at a second node in the bandgap circuit and for providing a second logic signal; and

a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal, wherein the first replica branch is a replica of a core branch in the bandgap circuit and comprises a transistor, resistor and diode coupled in series between a supply voltage and a circuit ground.

2. The bandgap ready circuit of claim 1 wherein the bandgap circuit comprises first and second current mirrors.

3. The bandgap ready circuit of claim 2 wherein the first current mirror comprises an N-channel current mirror.

4. The bandgap ready circuit of claim 2 wherein the second current mirror comprises a P-channel current mirror.

5. The bandgap ready circuit of claim 2 wherein the first comparator is coupled to the first current mirror.

6. The bandgap ready circuit of claim 2 wherein the second comparator is coupled to the second current mirror.

7. The bandgap ready circuit of claim 1 wherein the logic circuit comprises an AND gate.

8. The bandgap ready circuit of claim 1 wherein the second logic signal comprises a signal to indicate saturation operation of the bandgap circuit.

9. A method of monitoring a bandgap circuit for providing a bandgap voltage comprising:

monitoring a first voltage in a first replica branch in the bandgap circuit and a second voltage at a first node in the bandgap circuit and for providing a first logic signal;

monitoring a third voltage in a second replica branch in the bandgap circuit and a fourth voltage at a second node in the bandgap circuit and for providing a second logic signal; and

combining the first and second logic signals to provide a bandgap ready logic signal, wherein the first replica branch is a replica of a core branch in the bandgap circuit and comprises a transistor, resistor and diode coupled in series between a supply voltage and a circuit ground.

10. The method of claim 9 wherein the bandgap circuit comprises first and second current mirrors.

11. The method of claim 10 wherein the first current mirror comprises an N-channel current mirror.

12. The method of claim 10 wherein the second current mirror comprises a P-channel current mirror.

13. The method of claim 10 wherein the first comparator is coupled to the first current mirror.

14. The method of claim 10 wherein the second comparator is coupled to the second current mirror.

15. The method of claim 9 wherein the logic circuit comprises an AND gate.

20. The method of claim 9 wherein the second logic signal comprises a signal to indicate saturation operation of the bandgap circuit.

16. A bandgap ready circuit comprising:

a bandgap circuit for providing a bandgap voltage including first and second current mirrors;

a first replica branch and a second replica branch;

a first comparator for monitoring a first voltage in the first replica branch and a second voltage in the first current mirror, and providing a first logic signal;

a second comparator for monitoring a third voltage in the second replica branch and a fourth voltage in the second current mirror, and providing a second logic signal; and

a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal,

wherein the first replica branch is a replica of a core branch in the bandgap circuit and comprises a transistor, resistor and diode coupled in series between a supply voltage and a circuit ground.

17. The bandgap ready circuit of claim 16 wherein the first current mirror comprises an N-channel current mirror.

18. The bandgap ready circuit of claim 16 wherein the second current mirror comprises a P-channel current mirror.

19. The bandgap ready circuit of claim 16 wherein the logic circuit comprises an AND gate.