Capacitive charge pump

• US 8,823,380 B2
• Filed: 06/30/2011
• Issued: 09/02/2014
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Levine, Peter, Milgrew, Mark, Rearick, Todd
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): Rhodes-Vivour, Temilade S
• Application Number:
  US13/174,233
• Publication Number:
  US 20120001685A1
• Time in Patent Office: 1,160 Days
• Field of Search: 324/71.5, 324/762.09, 324/FOR.119, 324/425, 204/403.01, 204/403.14, 204/406, 204/412, 204/433, 205/775, 205/793.5
• US Class Current: 324/425
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

One or more charge pumps may be used to amplify the output voltage from a chemically-sensitive pixel that comprises one or more transistors. A charge pump may include a number of track stage switches, a number of boost phase switches and a number of capacitors. The capacitors are in parallel during the track phase and in series during the boost phase, and the total capacitance is divided during the boost phase while the total charge remains fixed. Consequently, the output voltage is pushed up.

Claims

1. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs), chemFETs in the array including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer;

a plurality of column lines and a plurality of row lines coupled to chemFETs in the array of chemFETs; and

circuitry coupled to the plurality of column lines and the plurality of row lines for reading a selected chemFET coupled to a selected column line and a selected row line, the circuitry comprising;

bias circuitry to apply a read voltage to the selected row line during a read interval; and

charge pump circuitry comprising;

a plurality of capacitors;

a first set of switches responsive to a first switching signal to connect the plurality of capacitors in parallel to sample a voltage level on the selected column line at a circuit node during a first stage of the read interval; and

a second set of switches responsive to a second switching signal to connect the plurality of capacitors in series to amplify the sampled voltage level at the circuit node during a second stage of the read interval.

2. The device of claim 1, wherein the sampled voltage level on the selected column line indicates an ion-concentration of an analyte solution exposed to the passivation layer during the read interval.

3. The device of claim 1, wherein the charge pump circuitry further comprises a source follower circuit having an input coupled to the circuit node.

4. The device of claim 1, wherein the charge pump circuitry further comprises:

a second plurality of capacitors;

a third set of switches responsive to a third switching signal to connect the second plurality of capacitors in parallel to sample the amplified voltage level on the circuit node at a second circuit node during a third stage of the read interval; and

a fourth set of switches responsive to a fourth switching signal to connect the second plurality of capacitors in series to further amplify the sampled voltage level at the second circuit node during a fourth stage of the read interval.

5. The device of claim 1, wherein the second set of switches includes a switch to sample the amplified voltage level on the circuit node at a second circuit node during the second stage of the read interval, and the charge pump circuitry further comprises a feedback path between the circuit node and the second circuit node, the feedback path including:

a buffer amplifier having an input coupled to the second circuit node, and having an output; and

a feedback switch between the output of the buffer amplifier and the circuit node, the feedback switch responsive to a third switching signal to connect the output of the buffer amplifier to the circuit node to feedback the sampled amplified voltage level at the second circuit node to the circuit node during a third stage of the read interval.

6. The device of claim 5, wherein:

the first switching signal connects the plurality of capacitors in parallel during the third stage of the read interval; and

the second switching signal connects the plurality of capacitors in parallel during a fourth stage of the read interval, thereby further amplifying the voltage level at the circuit node.

7. The device of claim 1, wherein the plurality of capacitors includes at least three capacitors.

8. A method for reading a selected chemically-sensitive field effect transistor (chemFET) including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer, the selected chemFET coupled to a selected column line and a selected row line, the method comprising:

applying a read voltage to the selected row line during a read interval;

connecting a plurality of capacitors in parallel to sample a voltage level on the selected column line at a circuit node during a first stage of the read interval; and

connecting the plurality of capacitors in series to amplify the sampled voltage level at the circuit node during a second stage of the read interval.

9. The method of claim 8, wherein the sampled voltage level on the selected column line indicates an ion-concentration of an analyte solution exposed to the passivation layer during the read interval.

10. The method of claim 8, further comprising:

connecting a second plurality of capacitors in parallel to sample the amplified voltage level on the circuit node at a second circuit node during a third stage of the read interval; and

connecting the second plurality of capacitors in parallel to further amplify the sampled voltage level at the second circuit node during a fourth stage of the read interval.

11. The method of claim 8, further comprising:

sampling the amplified voltage level on the circuit node at a second node during the second stage of the read interval;

connecting the plurality of capacitors in parallel during a third stage of the read interval, and establishing a feedback path to set the sampled amplified voltage level at the second circuit node on the circuit node during the third stage; and

connecting the plurality of capacitors in series during a fourth stage of the read interval, thereby further amplifying the voltage level at the circuit node.

12. The method of claim 8, wherein the plurality of capacitors includes at least three capacitors.