Fully complementary self-biased differential receiver with startup circuit

• US 8,823,454 B2
• Filed: 03/30/2012
• Issued: 09/02/2014
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sanchez, Hector
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US13/435,981
• Publication Number:
  US 20130257513A1
• Time in Patent Office: 886 Days
• Field of Search: 330/253, 330/259, 330/261
• US Class Current: 330/261
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/7227 the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45381 Long tailed pairs H03F3/45408, H03F3/45434 take precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

In accordance with at least one embodiment, an improved voltage headroom self-biased receiver is provided. In accordance with at least one embodiment, tail current sources are biased so as to be cross-coupled with respect to each other. In accordance with at least one embodiment, startup control is provided to counter defect-induced current and to ensure the circuit can function properly even with large amounts of defect current. In accordance with at least one embodiment, a positive type (p type) channel metal oxide semiconductor (PMOS) tail current transistor is modulated by a negative type (n type) channel metal oxide semiconductor (NMOS) differential pair virtual negative supply voltage and a NMOS tail current transistor is modulated by a PMOS differential pair virtual positive supply voltage. The amplifier'"'"'s output common mode is thus self correcting to p type to n type transistor strength differences.

Claims

1. A method for operating a differential receiver comprising:

modulating a tail current transistor of a first conductivity type by a virtual negative supply voltage, wherein the tail current transistor of the first conductivity type is situated between a positive supply voltage and a virtual positive supply voltage; and

modulating a tail current transistor of a second conductivity type by the virtual positive supply voltage, wherein the tail current transistor of the second conductivity type is situated between the virtual negative supply voltage and a negative supply voltage.

2. The method of claim 1 further comprising:

receiving a first enable signal at a first enable input, the first enable input coupled to a first tail current source enable transistor, wherein the first tail current source enable transistor enables flow of a first portion of a total amount of tail current, wherein the first tail current source enable transistor is coupled to an element selected from a group consisting of the tail current transistor of the first conductivity type and the tail current transistor of the second conductivity type; and

receiving a second enable signal at a second enable input, the second enable input coupled to a second tail current source enable transistor, wherein the second tail current source enable transistor enables flow of a second portion of the total amount of tail current.

3. The method of claim 1 further comprising:

providing a startup circuit coupled to the virtual positive supply voltage and to the virtual negative supply voltage to provide tolerance of defect current.

4. The method of claim 1 further comprising:

coupling the virtual positive supply voltage to a first terminal of a metal oxide semiconductor (MOS) transistor;

coupling the virtual negative supply voltage to a second terminal of the MOS transistor; and

coupling a negative supply voltage to a third terminal of the MOS transistor.

5. The method of claim 4 further comprising:

providing an enable circuit situated between the tail current transistor of the second conductivity type and the negative supply voltage.

6. The method of claim 4 further comprising:

providing an enable circuit situated between the tail current transistor of the first conductivity type and the positive supply voltage.

7. The method of claim 4 further comprising:

coupling the positive supply voltage to the body of the MOS transistor,

wherein the coupling the virtual positive supply voltage to the first terminal of the MOS transistor further comprises;

coupling the virtual positive supply voltage to the gate of the MOS transistor,

wherein the coupling the virtual negative supply voltage to the second terminal of the MOS transistor further comprises;

coupling the virtual negative supply voltage to the source of the MOS transistor, and

wherein the coupling the negative supply voltage to the third terminal of the MOS transistor further comprises;

coupling the negative supply voltage to the drain of the MOS transistor.

8. A method for operating a fully differential and complementary topology comprising:

coupling a first terminal selected from a group consisting of a source, a drain, a gate, and a body of a field effect transistor (FET) to the virtual positive supply voltage;

coupling a second terminal selected from the group consisting of the source, the drain, the gate, and the body of the FET to the virtual negative supply voltage;

coupling a third terminal selected from the group consisting of the source, the drain, the gate, and the body of the FET to a positive supply voltage;

coupling a fourth terminal selected from the group consisting of the source, the drain, the gate, and the body of the FET to a negative supply voltage;

referencing a positive tail current source to a virtual negative supply rail voltage associated with a negative tail current source; and

referencing the negative tail current source to a virtual positive supply rail voltage associated with the positive tail current source.

9. The method of claim 8 wherein the referencing the positive tail current source to the virtual negative supply rail voltage associated with the negative tail current source further comprises:

coupling the virtual negative supply rail voltage to the gate of a positive tail current source positive metal oxide semiconductor (PMOS) transistor, wherein the drain of the positive tail current source PMOS transistor is coupled to the virtual positive supply rail voltage; and

wherein the referencing the negative tail current source to the virtual positive supply rail voltage associated with the positive tail current source further comprises;

coupling the virtual positive supply rail voltage to the gate of a negative tail current source negative metal oxide semiconductor (NMOS) transistor, wherein the drain of the negative tail current source NMOS transistor is coupled to the virtual negative supply rail voltage.

10. The method of claim 9 wherein the source of the positive tail current source PMOS transistor is coupled to a positive supply rail voltage and the source of the negative tail current source NMOS transistor is coupled to a negative supply rail voltage.

11. The method of claim 8 wherein said coupling said first terminal, coupling said second terminal, coupling said third terminal, and coupling said fourth terminal increase defect current tolerance.

12. A self-biased receiver comprising:

a positive supply voltage coupled to a positive tail current source, the positive tail current source providing a virtual positive supply voltage;

a negative supply voltage coupled to a negative tail current source, the negative tail current source providing a virtual negative supply voltage;

a differential amplifier comprising a positive driver portion coupled to the virtual positive supply voltage and a negative driver portion coupled to the virtual negative supply voltage, the virtual positive supply voltage controlling the negative tail current source, and the virtual negative supply voltage controlling the positive tail current source; and

a startup circuit, the startup circuit coupled to the virtual positive supply voltage and to the virtual negative supply voltage.

13. The self-biased receiver of claim 12 wherein the positive tail current source comprises:

a positive metal oxide semiconductor (PMOS) transistor, wherein the gate of the PMOS transistor is coupled to the virtual negative supply voltage, wherein the source of the PMOS transistor is coupled to the positive supply voltage, and wherein the drain of the PMOS transistor is coupled to the virtual positive supply voltage.

14. The self-biased receiver of claim 13 wherein the negative tail current source comprises:

a negative metal oxide semiconductor (NMOS) transistor, wherein the gate of the NMOS transistor is coupled to the virtual positive supply voltage, wherein the source of the NMOS transistor is coupled to the negative supply voltage, and wherein the drain of the NMOS transistor is coupled to the virtual negative supply voltage.

15. The self-biased receiver of claim 14 further comprising:

an enable circuit, wherein the enable circuit selectively couples the source of the NMOS transistor to the negative supply voltage.

16. The self-biased receiver of claim 12 wherein the startup circuit further comprises:

a metal oxide semiconductor (MOS) transistor, wherein a first terminal of the MOS transistor is coupled to the virtual positive supply voltage, wherein a second terminal of the MOS transistor is coupled to the virtual negative supply voltage, wherein a third terminal of the MOS transistor is coupled to the negative supply voltage, and wherein a fourth terminal of the MOS transistor is coupled to the positive supply voltage.

17. The self-biased receiver of claim 16 wherein the MOS transistor further comprises:

a second PMOS transistor, wherein the gate of the second PMOS transistor is coupled to the virtual positive supply voltage, wherein the source of the second PMOS transistor is coupled to the virtual negative supply voltage, wherein the drain of the second PMOS transistor is coupled to the negative supply voltage, and wherein the body of the second PMOS transistor is coupled to the positive supply voltage.

18. The self-biased receiver of claim 12 wherein the startup circuit provides a defect current tolerance of at least three microamperes.

19. A method for operating a differential receiver comprising:

modulating a tail current transistor of a first conductivity type by a virtual negative supply voltage;

modulating a tail current transistor of a second conductivity type by a virtual positive supply voltage; and

providing a startup circuit coupled to the virtual positive supply voltage and to the virtual negative supply voltage to provide tolerance of defect current.