Liquid crystal display device and method for driving the same

• US 8,823,754 B2
• Filed: 04/01/2011
• Issued: 09/02/2014
• Est. Priority Date: 04/09/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Miyake, Hiroyuki, Yamazaki, Shunpei
• Primary Examiner(s): Bolotin, Dmitriy
• Application Number:
  US13/078,206
• Publication Number:
  US 20110248978A1
• Time in Patent Office: 1,250 Days
• Field of Search: 345 87-103, 345204-215, 345690-699
• US Class Current: 345/690
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/3413 Details of control of colour illumination sources
• CPC Class Codes: G09G 3/3426 the different display panel areas being distributed in two dimensions, e.g. matrix
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

To increase the frequency of input of image signals in terms of design in a field-sequential liquid crystal display device. Image signals are concurrently supplied to pixels provided in a plurality of rows among pixels arranged in matrix in a pixel portion of the liquid crystal display device. Thus, the frequency of input of an image signal to each pixel can be increased without change in response speed of a transistor or the like included in the liquid crystal display device.

Claims

1. A display device comprising:

a first signal line provided so as to be supplied with a first image signal in a first horizontal scan period which is included in a first sampling period, and supplied with a second image signal in a second horizontal scan period which is included in a second sampling period;

a second signal line provided so as to be supplied with a third image signal in the first horizontal scan period, and supplied with a fourth image signal in the second horizontal scan period;

a first scan line and a second scan line which are provided so as to be supplied with a selection signal in the first horizontal scan period, and supplied with a non-selection signal in the second horizontal scan period;

a third scan line and a fourth scan line which are provided so as to be supplied with a non-selection signal in the first horizontal scan period, and supplied with a selection signal in the second horizontal scan period;

a first pixel electrically connected to the first signal line, the second signal line, the first scan line, and the third scan line, wherein the first pixel is provided so as to be supplied with the first image signal in the first horizontal scan period, and supplied with the fourth image signal in the second horizontal scan period;

a second pixel electrically connected to the first signal line, the second signal line, the second scan line, and the fourth scan line, wherein the second pixel is provided so as to be supplied with the third image signal in the first horizontal scan period, and supplied with the second image signal in the second horizontal scan period;

a first shift register configured to supply a selection signal to the first scan line in the first horizontal scan period and supply a selection signal to the fourth scan line in the second horizontal scan period; and

a second shift register configured to supply a selection signal to the second scan line in the first horizontal scan period and supply a selection signal to the third scan line in the second horizontal scan period.

2. The display device according to claim 1,

wherein the first pixel includes:

a first transistor, wherein a gate of the first transistor is electrically connected to the first scan line, and one of a source and a drain of the first transistor is electrically connected to the first signal line;

a second transistor, wherein a gate of the second transistor is electrically connected to the third scan line, and one of a source and a drain of the second transistor is electrically connected to the second signal line; and

a first liquid crystal element, wherein one electrode of the first liquid crystal element is electrically connected to the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor,

wherein the second pixel includes;

a third transistor, wherein a gate of the third transistor is electrically connected to the fourth scan line, and one of a source and a drain of the third transistor is electrically connected to the first signal line;

a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the second scan line, and one of a source and a drain of the fourth transistor is electrically connected to the second signal line; and

a second liquid crystal element, wherein one electrode of the second liquid crystal element is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and

wherein each of the first to fourth transistors includes a channel formation region including an oxide semiconductor.

3. The display device according to claim 1, wherein each of the first shift register and the second shift register includes a transistor which includes a channel formation region including an oxide semiconductor.

4. A display device comprising:

a first signal line provided so as to be supplied with a first image signal in a first horizontal scan period which is included in a first sampling period, supplied with a second image signal in a second horizontal scan period which is included in a second sampling period, and supplied with a third image signal in a third horizontal scan period which is included in a third sampling period;

a second signal line provided so as to be supplied with a fourth image signal in the first horizontal scan period, supplied with a fifth image signal in the second horizontal scan period, and supplied with a sixth image signal in the third horizontal scan period;

a third signal line provided so as to be supplied with a seventh image signal in the first horizontal scan period, supplied with an eighth image signal in the second horizontal scan period, and supplied with a ninth image signal in the third horizontal scan period;

a first scan line, a fifth scan line, and a ninth scan line which are provided so as to be supplied with a selection signal in the first horizontal scan period;

a third scan line, a fourth scan line, and an eighth scan line which are provided so as to be supplied with a selection signal in the second horizontal scan period;

a second scan line, a sixth scan line, and a seventh scan line which are provided so as to be supplied with a selection signal in the third horizontal scan period;

a first pixel electrically connected to the first signal line, the second signal line, the third signal line, the first scan line, the second scan line, and the third scan line,

a second pixel electrically connected to the first signal line, the second signal line, the third signal line, the fourth scan line, the fifth scan line, and the sixth scan line,

a third pixel electrically connected to the first signal line, the second signal line, the third signal line, the seventh scan line, the eighth scan line, and the ninth scan line,

a first shift register electrically connected to the first scan line, the fourth scan line, and the seventh scan line;

a second shift register electrically connected to the second scan line, the fifth scan line, and the eighth scan line; and

a third shift register electrically connected to the third scan line, the sixth scan line, and the ninth scan line.

5. The display device according to claim 4,

wherein the first pixel comprises:

a first transistor, wherein a gate of the first transistor is electrically connected to the first scan line, and one of a source and a drain of the first transistor is electrically connected to the first signal line;

a second transistor, wherein a gate of the second transistor is electrically connected to the second scan line, and one of a source and a drain of the second transistor is electrically connected to the second signal line;

a third transistor, wherein a gate of the third transistor is electrically connected to the third scan line, and one of a source and a drain of the third transistor is electrically connected to the third signal line; and

a first liquid crystal element, wherein one of electrodes of the first liquid crystal element is electrically connected to the other of the source and the drain of the first transistor, the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor,

wherein the second pixel comprises;

a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the fourth scan line, and one of a source and a drain of the fourth transistor is electrically connected to the first signal line;

a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the fifth scan line, and one of a source and a drain of the fifth transistor is electrically connected to the second signal line;

a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the sixth scan line, and one of a source and a drain of the sixth transistor is electrically connected to the third signal line; and

a second liquid crystal element, wherein one of electrodes of the second liquid crystal element is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, and the other of the source and the drain of the sixth transistor, and

wherein the third pixel comprises;

a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the seventh scan line, and one of a source and a drain of the seventh transistor is electrically connected to the first signal line;

an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the eighth scan line, and one of a source and a drain of the eighth transistor is electrically connected to the second signal line;

a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the ninth scan line, and one of a source and a drain of the ninth transistor is electrically connected to the third signal line; and

a third liquid crystal element, wherein one of electrodes of the third liquid crystal element is electrically connected to the other of the source and the drain of the seventh transistor, the other of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor,

wherein each of the first to ninth transistors includes a channel formation region including an oxide semiconductor.

6. The display device according to claim 4, wherein each of the first shift register and the second shift register includes a transistor which includes a channel formation region including an oxide semiconductor.

7. A method for driving a display device comprising the steps of:

in a sampling period in which an image signal is input to a plurality of pixels in a first to n-th rows (n is a natural number of 3 or more) while an image signal is input to a plurality of pixels in an (n+1)th to 2n-th rows,

after finishing inputting the image signal to the plurality of pixels in the first to k-th rows (k is a natural number of 2 or more and less than n) while inputting the image signal to the plurality of pixels in the (n+1)th to (n+k)th rows during a first period, making a light source for the first to k-th rows and a light source for the (n+1)th to (n+k)th rows emit light having a first color and a second color, respectively, during a third period; and

after finishing inputting the image signal to the plurality of pixels in the (k+1)th to 2k-th rows while inputting the image signal to the plurality of pixels in the (n+k+1)th to (n+2k)th rows during a second period, making a light source for the (k+1)th to 2k-th rows and a light source for the (n+k+1)th to (n+2k)th rows emit light having the first color and the second color, respectively, during a fourth period,

wherein a part of the third period is overlapped with a part of the fourth period.

8. The method for driving a display device according to claim 7,

wherein a part of the second period is overlapped with a part of the third period.

9. The method for driving a display device according to claim 7,

wherein the first color is white, cyan, magenta, or yellow.

10. The method for driving a display device according to claim 7,

wherein the image signal is input to each of the plurality of pixels in a first to 2n-th rows through a transistor including an oxide semiconductor.