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Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof

  • US 8,824,191 B2
  • Filed: 08/22/2013
  • Issued: 09/02/2014
  • Est. Priority Date: 06/08/2010
  • Status: Active Grant
First Claim
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1. A method of operating a re-programmable non-volatile memory system, comprising:

  • utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which comprises;

    a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;

    a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;

    a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;

    a plurality of non-volatile re-programmable memory elements individually connected between the bit line pillars and the word lines adjacent the crossings thereof;

    wherein the memory elements form a population with properties that when a bias voltage being applied to the memory elements is;

    at a level Vset_min, some memory elements of the population will begin to be set from a higher resistance state to a lower resistance state in a unipolar or bipolar mode; and

    at a level Vset_max greater than Vset_min, practically the entire population is set;

    at a level Vrst_min_uni, some memory elements of the population will begin to be reset in a unipolar mode from the lower resistance state to the higher resistance state; and

    at a level Vrst_max_uni greater than Vrst_min_uni and less than Vset_min, practically the entire population is reset; and

    at a negative level Vrst_min_bip, some memory elements of the population will begin to be reset in a bipolar mode from the lower resistance state to the higher resistance state; and

    at a less negative level Vrst_max_bip than Vrst_min_bip, practically the entire population is reset; and

    setting a resistive state of a selected memory element from a higher resistance state to a lower resistance state in a bipolar mode or a unipolar mode by applying a bias voltage greater than the level Vset_max across a selected word line and a selected bit line without setting or resetting unselected memory elements by maintaining Vset_max−

    Vrst_min_uni<

    Vrst_min_uni+Vrst_min_bip.

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