Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof

• US 8,824,191 B2
• Filed: 08/22/2013
• Issued: 09/02/2014
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Samachisa, George, Fasoli, Luca, Li, Yan, Yan, Tianhong
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/973,218
• Publication Number:
  US 20140022848A1
• Time in Patent Office: 376 Days
• Field of Search: 365/148, 365/163, 365/185.21
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

Claims

1. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which comprises;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;

a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;

a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;

a plurality of non-volatile re-programmable memory elements individually connected between the bit line pillars and the word lines adjacent the crossings thereof;

wherein the memory elements form a population with properties that when a bias voltage being applied to the memory elements is;

at a level Vset_min, some memory elements of the population will begin to be set from a higher resistance state to a lower resistance state in a unipolar or bipolar mode; and

at a level Vset_max greater than Vset_min, practically the entire population is set;

at a level Vrst_min_uni, some memory elements of the population will begin to be reset in a unipolar mode from the lower resistance state to the higher resistance state; and

at a level Vrst_max_uni greater than Vrst_min_uni and less than Vset_min, practically the entire population is reset; and

at a negative level Vrst_min_bip, some memory elements of the population will begin to be reset in a bipolar mode from the lower resistance state to the higher resistance state; and

at a less negative level Vrst_max_bip than Vrst_min_bip, practically the entire population is reset; and

setting a resistive state of a selected memory element from a higher resistance state to a lower resistance state in a bipolar mode or a unipolar mode by applying a bias voltage greater than the level Vset_max across a selected word line and a selected bit line without setting or resetting unselected memory elements by maintaining Vset_max−

Vrst_min_uni<

Vrst_min_uni+Vrst_min_bip.

2. The method as in claim 1, further comprising:

resetting a resistive state of a selected memory element from a lower resistance state to a higher resistance state in a unipolar mode by applying a bias voltage of greater than the level Vrst_max_uni but less than the level Vset_min across a selected word line and a selected bit line.

3. The method as in claim 1, further comprising:

resetting a resistive state of a selected memory element from a lower resistance state to a higher resistance state in a bipolar mode by applying a bias voltage more negative than the level Vrst_max_bip.

4. The method as in claim 1, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a higher potential than the selected bit line during said setting.

5. The method as in claim 1, wherein the selected memory element is among a block of memory elements selected in parallel by the selected word line.

6. The method as in claim 2, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a higher potential than the selected bit line during said setting.

7. The method as in claim 2, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a lower potential than the selected bit line during said resetting.

8. The method as in claim 2, wherein the selected memory element is among a block of memory elements selected in parallel by the selected word line.

9. The method as in claim 3, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a higher potential than the selected bit line during said setting.

10. The method as in claim 3, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a lower potential than the selected bit line during said resetting.

11. The method as in claim 3, wherein the selected memory element is among a block of memory elements selected in parallel by the selected word line.

12. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which comprises;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;

a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction;

a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of bit line pillars in the individual planes, wherein the bit line pillars and word lines cross adjacent each other at a plurality of locations across the individual planes;

a plurality of non-volatile re-programmable memory elements individually connected between the bit line pillars and the word lines adjacent the crossings thereof;

wherein the memory elements form a population with properties that when a bias voltage being applied to the memory elements is;

at a level Vset_min, some memory elements of the population will begin to be set from a higher resistance state to a lower resistance state in a unipolar or bipolar mode; and

at a level Vset_max greater than Vset_min, practically the entire population is set;

at a level Vrst_min_uni, some memory elements of the population will begin to be reset in a unipolar mode from the lower resistance state to the higher resistance state; and

at a level Vrst_max_uni greater than Vrst_min_uni and less than Vset_min, practically the entire population is reset; and

at a negative level Vrst_min_bip, some memory elements of the population will begin to be reset in a bipolar mode from the lower resistance state to the higher resistance state; and

at a less negative level Vrst_max_bip than Vrst_min_bip, practically the entire population is reset; and

setting a resistive state of a selected memory element from a higher resistance state to a lower resistance state in a bipolar mode or a unipolar mode by applying a bias voltage of at least the level Vset_max across a selected word line and a selected bit line without setting or resetting unselected memory elements by maintaining Vset_max−

Vrst_min_uni<

Vrst_min_uni+Vrst_min_bip−

Δ

VWLs−

Δ

−

Δ

VWLu, where Δ

VWLs and Δ

VWLu are respectively the maximum voltage drop across the extent of the selected and unselected word lines of an adjacent pair of word lines.

13. The method as in claim 12, further comprising:

resetting a resistive state of a selected memory element from a lower resistance state to a higher resistance state in a unipolar mode by applying a bias voltage of at least Vrst_max_uni+Δ

VWLs but less than Vset_min−

Δ

VWLu across a selected word line and a selected bit line.

14. The method as in claim 12, further comprising:

resetting a resistive state of a selected memory element from a lower resistance state to a higher resistance state in a bipolar mode by applying a bias voltage at least as negative as the level Vrst_max_bip+Δ

VWLs.

15. The method as in claim 12, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a higher potential than the selected bit line during said setting.

16. The method as in claim 12, wherein the selected memory element is among a block of memory elements selected in parallel by the selected word line.

17. The method as in claim 13, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a higher potential than the selected bit line during said setting.

18. The method as in claim 13, wherein the bias voltage is applied across the selected word line and selected bit line with the selected word line being at a lower potential than the selected bit line during said resetting.

19. The method as in claim 13, wherein the selected memory element is among a block of memory elements selected in parallel by the selected word line.