Semiconductor device and method for driving the same

• US 8,824,194 B2
• Filed: 05/16/2012
• Issued: 09/02/2014
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kobayashi, Hidetomo, Shionoiri, Yutaka, Nishijima, Tatsuji
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US13/472,741
• Publication Number:
  US 20120294067A1
• Time in Patent Office: 839 Days
• Field of Search: 365/149, 365/205
• US Class Current: 365/149
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a semiconductor device performing pipeline processing with the use of a reading portion reading an instruction and an arithmetic portion performing an operation in accordance with the instruction, the instruction held in the reading portion is transmitted from the flip-flop to the memory when branch prediction turns out to be wrong. Note that the arithmetic portion controls transmission and reception of the instruction between the flip-flop and the memory which are included in the reading portion. This enables elimination of redundant operations in the reading portion in the case where an instruction read by the reading portion after the branch prediction turns out to be wrong is a subroutine, or the like. That is, the instruction held in the memory is transmitted back to the flip-flop without rereading of the same instruction by the reading portion, whereby the instruction can be output to the arithmetic portion.

Claims

1. A semiconductor device comprising:

a first portion configured to read an instruction; and

a second portion configured to perform an operation in accordance with the instruction,

wherein the first portion comprises;

a flip-flop configured to read and hold the instruction;

a memory configured to receive the instruction from the flip-flop, and transmit the instruction to the flip-flop; and

a third portion configured to correct the instruction held in the memory or the instruction transmitted from the memory to the flip-flop in accordance with the operation performed by the second portion while the instruction is held in the memory, and

wherein reception and transmission of the instruction between the flip-flop and the memory are controlled with a signal output by the second portion.

2. The semiconductor device according to claim 1,

wherein the memory comprises:

a transistor in which a channel is formed in an oxide semiconductor; and

a capacitor,

wherein one of a source and a drain of the transistor is electrically connected to the flip-flop,

wherein the other of the source and the drain of the transistor is electrically connected to one of electrodes of the capacitor, and

wherein a gate of the transistor is electrically connected to the second portion.

3. A method for driving the semiconductor device according to claim 1, comprising:

reading a first instruction by the first portion;

transmitting the first instruction from the flip-flop to the memory;

reading a second instruction by the first portion;

operating by the second portion in accordance with the second instruction;

transmitting back the first instruction from the memory to the flip-flop; and

operating by the second portion in accordance with the first instruction.

4. A semiconductor device comprising:

a first portion configured to read an instruction; and

a second portion configured to perform an operation in accordance with the instruction,

wherein the first portion comprises;

a flip-flop configured to read and hold the instruction; and

a memory configured to receive the instruction from the flip-flop, and transmit the instruction to the flip-flop,

wherein reception and transmission of the instruction between the flip-flop and the memory are controlled with a signal output by the second portion,

wherein the memory comprises;

a first transistor in which a channel is formed in an oxide semiconductor;

a first capacitor;

a second transistor; and

a second capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to the flip-flop,

wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the first capacitor,

wherein a gate of the first transistor is electrically connected to the second portion,

wherein one of a source and a drain of the second transistor is electrically connected to the flip-flop,

wherein the other of the source and the drain of the second transistor is electrically connected to one of electrodes of the second capacitor, and

wherein a gate of the second transistor is electrically connected to a power supply.

5. The semiconductor device according to claim 4,

wherein a capacitance value of the second capacitor is larger than a capacitance value of the first capacitor.

6. A method for driving the semiconductor device according to claim 4, comprising:

reading a first instruction by the first portion;

transmitting the first instruction from the flip-flop to the memory;

reading a second instruction by the first portion;

operating by the second portion in accordance with the second instruction;

transmitting back the first instruction from the memory to the flip-flop; and

operating by the second portion in accordance with the first instruction.