Non-volatile memory device having vertical structure and method of operating the same
First Claim
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1. A method of programming a non-volatile memory device including a plurality of memory cell strings arranged in rows and columns, columns of the plurality of memory cell strings being coupled with a plurality of bit lines respectively, the method comprising:
- applying a turn-on voltage to gates of at least two first select transistors of a first memory cell string among the plurality of memory cell strings, the at least two first select transistors being stacked in series along a direction vertical to a substrate;
applying a pass voltage or a program voltage to respective gates of memory cells of the first cell string, the memory cells being stacked in series along the direction vertical to the substrate between the substrate and a side of the at least two first select transistors;
applying a first voltage to at least one gate of at least one dummy memory cell of the first cell string, the at least one dummy memory cell being stacked in series along the direction vertical to the substrate between a side of the at least two first select transistors and a side of the memory cells; and
applying a ground voltage to a bit line coupled to the first memory cell string if one of the memory cells of the first cell string are to be programmed,wherein the first voltage is lower than the pass voltage and the program voltage and higher than a ground voltage.
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Abstract
Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.
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Citations
18 Claims
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1. A method of programming a non-volatile memory device including a plurality of memory cell strings arranged in rows and columns, columns of the plurality of memory cell strings being coupled with a plurality of bit lines respectively, the method comprising:
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applying a turn-on voltage to gates of at least two first select transistors of a first memory cell string among the plurality of memory cell strings, the at least two first select transistors being stacked in series along a direction vertical to a substrate; applying a pass voltage or a program voltage to respective gates of memory cells of the first cell string, the memory cells being stacked in series along the direction vertical to the substrate between the substrate and a side of the at least two first select transistors; applying a first voltage to at least one gate of at least one dummy memory cell of the first cell string, the at least one dummy memory cell being stacked in series along the direction vertical to the substrate between a side of the at least two first select transistors and a side of the memory cells; and applying a ground voltage to a bit line coupled to the first memory cell string if one of the memory cells of the first cell string are to be programmed, wherein the first voltage is lower than the pass voltage and the program voltage and higher than a ground voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of programming a non-volatile memory device including first and second memory cell groups and first and second select transistor groups coupled between the first and second memory cell groups and a bit line, the method comprising:
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applying a first voltage to respective gates of at least two first select transistors of the first select transistor group coupled between the first memory cell group and the bit line, the at least two first select transistors being stacked in series along a direction vertical to a substrate; and applying a second voltage to respective gates of at least two second select transistors of the second select transistor group coupled between the second memory cell group and the bit line, the at least two second select transistors being stacked in series along the direction vertical to the substrate; applying a pass voltage or a program voltage to respective gates of first memory cells of the first memory cell group, the first memory cells being stacked in series along the direction vertical to the substrate; applying the pass voltage or the program voltage to respective gates of second memory cells of the second memory cell group, the second memory cells being stacked in series along the direction vertical to the substrate; applying a third voltage to at least one gate of at least one first dummy memory cell stacked in series along the direction vertical to the substrate between the first memory cell group and the first select transistor group; and applying a fourth voltage to at least one gate of at least one second dummy memory cell stacked in series along the direction vertical to the substrate between the second memory cell group and the second select transistor group, wherein the first voltage is lower than the program voltage and higher than a ground voltage, wherein the second voltage is lower than the first voltage. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A solid state drive comprising:
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a nonvolatile memory including a plurality of nonvolatile memory groups, each of the plurality of nonvolatile memory groups including a plurality of nonvolatile memory chips; and a controller configured to communicate with the plurality of nonvolatile memory groups through a plurality of channels respectively, select a channel from among the plurality of channels, and output a program command, data and an address to the selected channel, wherein each of the nonvolatile memory chips includes; a memory cell array; a page buffer configured to store received data and apply first bias voltages to the memory cell array according to the stored data and received program command; and a row decoder configured to apply second bias voltages to the memory cell array according to received address and the received program command, wherein the memory cell array includes; a substrate; a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked in series along a direction vertical to the substrate; a plurality of first select transistor groups coupled between the substrate and the plurality of memory cell groups respectively, each first select transistor group including at least one first select transistor stacked in series along the direction vertical to the substrate; and a plurality of second select transistor groups coupled between the plurality of memory cell groups and a plurality of bit lines respectively, each second select transistor group including at least two second select transistors stacked in series along the direction vertical to the substrate, wherein the row decoder applies a turn-on voltage to respective gates of second select transistors of a selected row of the plurality of first select transistor groups and apply a turn-off voltage to respective gates of second select transistors of unselected rows of the plurality of first select transistors according to received address and the received program command. - View Dependent Claims (15, 16, 17, 18)
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Specification