Hybrid memory device, system including the same, and method of reading and writing data in the hybrid memory device

• US 8,824,221 B2
• Filed: 09/14/2012
• Issued: 09/02/2014
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Hwi, Cho, Geun-Hee, Nguyen, Duc
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/616,398
• Publication Number:
  US 20130077382A1
• Time in Patent Office: 718 Days
• Field of Search: 365/148, 365/163, 365/189.02, 365/185.08, 365/185.23, 365/51, 365/63, 365/189.2
• US Class Current: 365/189.2
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A hybrid memory device is provided. The hybrid memory device includes a DRAM, a non-volatile memory and a control circuit. The control circuit selects one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected data. The control circuit outputs data requested to be output from the DRAM when the data requested to be output is in the DRAM, and may output the data requested to be output from the non-volatile memory when the data requested to be output is in the non-volatile memory. Accordingly, the hybrid memory device has a high speed in a read and write operation, and has low power consumption.

Claims

1. A hybrid memory device comprising:

a dynamic random access memory (DRAM);

a non-volatile memory; and

a control circuit configured to select one of output data of the DRAM and output data of the non-volatile memory according to a mode selecting signal and output the selected output data, configured to determine whether data requested to be output is in the DRAM, configured to output the data requested to be output from the DRAM in response to determining that the data requested to be output is in the DRAM, and configured to output the data requested to be output from the non-volatile memory in response to determining that the data requested to be output is not in the DRAM,

wherein the control circuit is configured to output the output data of the non-volatile memory directly to an exterior of the hybrid memory device without storing the output data of the non-volatile memory in the DRAM.

2. The hybrid memory device according to claim 1, wherein the control circuit is configured to generate the mode selecting signal based on the output data of the DRAM and the output data of the non-volatile memory.

3. The hybrid memory device according to claim 1, wherein the control circuit is configured to generate the mode selecting signal based on values of an address table.

4. The hybrid memory device according to claim 1, wherein, in a write mode, the hybrid memory device is configured to unconditionally store data requested to be written to the DRAM.

5. The hybrid memory device according to claim 1, wherein the hybrid memory device is configured to store write-requested data in the DRAM after writing back a part of the write-requested data in the DRAM to the non-volatile memory, when a write request is received from a host and space in which the write-requested data is written is insufficient.

6. The hybrid memory device according to claim 5, wherein data which has not been used for a longest time among data in the DRAM is written back to the non-volatile memory.

7. The hybrid memory device according to claim 1, wherein the control circuit comprises:

a mode selecting circuit configured to generate the mode selecting signal based on the output data of the DRAM and the output data of the non-volatile memory; and

a multiplexer configured to select one of the output data of the DRAM and the output data of the non-volatile memory in response to the mode selecting signal.

8. The hybrid memory device according to claim 1, wherein the control circuit comprises:

a mode selecting circuit configured to generate the mode selecting signal based on values of an address table; and

a multiplexer configured to select one of the output data of the DRAM and the output data of the non-volatile memory in response to the mode selecting signal.

9. The hybrid memory device according to claim 8, wherein the control circuit further comprises:

an address buffer configured to determine the values of the address table based on an address received from a host.

10. The hybrid memory device according to claim 1, wherein the non-volatile memory includes a phase-change random access memory (PRAM) or a resistive random access memory (RRAM).

11. The hybrid memory device according to claim 1, wherein the DRAM, the non-volatile memory and the control circuit are implemented in a form of a multi-chip package (MCP).

12. The hybrid memory device according to claim 1, wherein the DRAM and the non-volatile memory are stacked three-dimensionally.

13. The hybrid memory device according to claim 12, wherein the DRAM and the non-volatile memory are configured to be electrically connected by a through-silicon-via (TSV).

14. A system comprising:

a host; and

a hybrid memory device comprising a control circuit configured to select one of output data of a dynamic random access memory (DRAM) and output data of a non-volatile memory according to a mode selecting signal and output the selected data, configured to determine whether data that the host requests to be output is in the DRAM, configured to output the data that the host requests to be output from the DRAM in response to determining that the data requested to be output is in the DRAM, and configured to output the data that the host requests to be output from the non-volatile memory in response to determining that the data requested to be output is not in the DRAM.

15. A hybrid memory device comprising:

a dynamic random access memory (DRAM);

a non-volatile memory;

a multiplexer connected to the DRAM and the non-volatile memory, and configured to select and output data from the DRAM or data from the non-volatile memory in response to a selection signal; and

a mode selecting circuit that generates the selection signal based on the data of the DRAM and the data of the non-volatile memory, or based on an address,

wherein the hybrid memory device is configured to determine whether data requested to be output is in the DRAM, configured to output the data requested to be output from the DRAM in response to determining that the data requested to be output is in the DRAM, and configured to output the data requested to be output from the non-volatile memory in response to determining that the data requested to be output is not in the DRAM,

wherein when the data from the non-volatile, memory is selected, the data from the non-volatile memory is output directly from the hybrid memory device without first being stored in the DRAM.

16. The hybrid memory device according to claim 15, wherein the hybrid memory device is a multi-chip package, and the DRAM is provided on a first chip, and the non-volatile memory is provided on a second chip which is different from the first chip.

17. The hybrid memory device according to claim 16, further comprising a substrate,

wherein the second chip is stacked on the first chip, and the first chip is stacked on the substrate.

18. The hybrid memory device according to claim 15, wherein the non-volatile memory is a phase-change random access memory (PRAM), a resistive random access memory (RRAM), or a flash memory.