Fast-wake memory

• US 8,824,222 B2
• Filed: 08/04/2011
• Issued: 09/02/2014
• Est. Priority Date: 08/13/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Zerbe, Jared L., Leibowitz, Brian S.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/702,112
• Publication Number:
  US 20130083611A1
• Time in Patent Office: 1,125 Days
• Field of Search: 365/191, 365/226, 365/227, 365/229, 713/323
• US Class Current: 365/191
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different-frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.

Claims

1. A method of operation within a memory controller, the method comprising:

outputting a first memory access command via a first command signaling interface in response to a first clock signal during an exit from a first power mode; and

outputting a second memory access command via a second command signaling interface in response to a second clock signal during a second power mode.

2. The method of claim 1 wherein the memory controller consumes more power in the second power mode than in the first power mode.

3. The method of claim 1 wherein the first clock signal has a lower frequency than the second clock signal.

4. The method of claim 1 wherein outputting a first memory access command via a first command signaling interface comprises outputting constituent bits of the first memory access command onto a first number of signaling links via a first number of output drivers, and wherein outputting a second memory access command via a second command signaling interface comprises outputting constituent bits of the second memory access command onto a second number of signaling links via a second number of output drivers, the first number being larger than the second number.

5. The method of claim 4 wherein each output driver included in the second number of output drivers is also included in the first number of output drivers, and wherein the first clock signal frequency is lower than the second clock signal frequency, and wherein a ratio of the first clock signal frequency to the second clock signal frequency is substantially equal to a ratio of the second number of output drivers to the first number of output drivers.

6. The method of claim 1 further comprising outputting write data via a data signaling interface during the second power mode, and wherein outputting the first memory access command via a first command signaling interface during an exit from a first power mode comprises outputting the first memory access command in part via the second command signaling interface and in part via the data signaling interface.

7. The method of claim 1 further comprising outputting write data during a data signaling interface and a mask value via a mask signaling interface during the second power mode, the mask value including bits that indicate whether or not respective portions of the write data are to be stored within a memory device, and wherein outputting the first memory access command via a first command signaling interface during an exit from a first power mode comprises outputting the first memory access command in part via the second command signaling interface and in part via the mask signaling interface.

8. A memory controller comprising:

a signaling interface that includes a plurality of output drivers;

clock circuitry to provide first and second clock signals to the signaling interface to time signal transmission operations within the plurality of output drivers; and

power mode circuitry to select the first clock signal to time output of a first memory access command via a first number of the output drivers within the signaling interface during an exit from a first power mode and to select the second clock signal to time output of a second memory access command via a second number of the output drivers within the signaling interface during a second power mode.

9. The memory controller of claim 8 wherein the first clock signal has a lower frequency than the second clock signal.

10. The memory controller of claim 8 wherein the first clock signal frequency is lower than the second clock signal frequency, and wherein a ratio of the first clock signal frequency to the second clock signal frequency is substantially equal to a ratio of the second number of the output drivers to the first number of the output drivers.

11. The memory controller of claim 8 wherein the signaling interface includes a third number of the output drivers to output write data during the second power mode, and the output drivers included in the third number of the output drivers are also included in the first number of the output drivers.

12. The memory controller of claim 8 wherein the signaling interface includes a third number of output drivers to output write data during the second power mode and an output driver to output a mask value corresponding to the write data during the second power mode, and wherein the output driver to output a mask value is included in the first number of output drivers.

13. A method of operation within a memory device, the method comprising:

receiving a first memory access command via a first command signaling interface in response to a first clock signal during an exit from a first power mode; and

receiving a memory access command via a second command signaling interface in response to a second clock signal during a second power mode.

14. The method of claim 13 wherein receiving a first memory access command via a first command signaling interface comprises receiving constituent bits of the first memory access command from a first number of signaling links via a first number of signal receivers, and wherein receiving a second memory access command via a second command signaling interface comprises receiving constituent bits of the second memory access command from a second number of signaling links via a second number of signal receivers, the first number being larger than the second number.

15. The method of claim 13 further comprising:

receiving first power mode information that indicates the exit from the first power mode; and

receiving second power mode information that indicates the second power mode.

16. A memory device comprising:

a signaling interface that includes a plurality of signal receivers;

clock circuitry to provide first and second clock signals to the signaling interface to time signal reception operations within the plurality of signal receivers; and

power mode circuitry to select the first clock signal to time reception of a first memory access command via a first number of the signal receivers within the signaling interface during an exit from a first power mode and to select the second clock signal to time reception of a second memory access command via a second number of the signal receivers within the signaling interface during a second power mode.

17. The memory device of claim 16 wherein the memory device consumes more power in the second power mode than in the first power mode.

18. The memory device of claim 16 wherein the first clock signal has a lower frequency than the second clock signal.

19. The memory device of claim 16 wherein the second number of the signal receivers is smaller than the first number of the signal receivers.

20. The memory device of claim 19 wherein at least one of the signal receivers included in the first number of the signal receivers is also included in the second number of the signal receivers.