Frequency-agile strobe window generation
First Claim
1. An integrated circuit, comprising:
- a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path on a memory device, wherein the timing signal includes a delay caused by the read path,wherein the timing circuit comprises;
a first programmable adjustment circuit to track the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and
a second calibration circuit to track the timing-enable signal with respect to a second delay in the delay; and
wherein the timing-enable signal provides an enable window for the timing signal to receive read data returned through the read path.
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Abstract
The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.
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Citations
50 Claims
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1. An integrated circuit, comprising:
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a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path on a memory device, wherein the timing signal includes a delay caused by the read path, wherein the timing circuit comprises; a first programmable adjustment circuit to track the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and a second calibration circuit to track the timing-enable signal with respect to a second delay in the delay; and wherein the timing-enable signal provides an enable window for the timing signal to receive read data returned through the read path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method for operating a memory controller, comprising:
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receiving a timing signal returned from a read path on a memory device, wherein the timing signal includes a delay caused by the read path; calibrating a timing-enable signal based on the timing signal by; synchronizing the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and synchronizing the timing-enable signal with respect to a second delay in the delay; using the calibrated timing-enable signal to enable the timing signal; and receiving read data returned through the read path using the enabled timing signal. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A memory controller, comprising:
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a timing circuit to synchronize a timing-enable signal with a timing signal associated with a read access, wherein the timing signal includes a delay, wherein the timing circuit further comprises; a first programmable adjustment circuit to track the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and a second programmable adjustment circuit to track the timing-enable signal with respect to a second delay in the delay; and wherein the timing-enable signal provides an enable window for the timing signal to retime read data associated with the read access.
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50. A method for operating a memory controller, comprising:
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receiving a timing signal associated with a read access, wherein the timing signal includes a delay; calibrating a timing-enable signal based on the timing signal by; synchronizing the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and synchronizing the timing-enable signal with respect to a second delay in the delay; using the calibrated timing-enable signal to enable the timing signal; and receiving read data associated with the read access using the enabled timing signal.
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Specification