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Frequency-agile strobe window generation

  • US 8,824,224 B2
  • Filed: 07/10/2012
  • Issued: 09/02/2014
  • Est. Priority Date: 08/05/2011
  • Status: Active Grant
First Claim
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1. An integrated circuit, comprising:

  • a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path on a memory device, wherein the timing signal includes a delay caused by the read path,wherein the timing circuit comprises;

    a first programmable adjustment circuit to track the timing-enable signal with respect to a first delay in the delay, wherein the first delay depends on a frequency of the timing signal; and

    a second calibration circuit to track the timing-enable signal with respect to a second delay in the delay; and

    wherein the timing-enable signal provides an enable window for the timing signal to receive read data returned through the read path.

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