SLC-MLC combination flash storage device

• US 8,825,941 B2
• Filed: 06/25/2009
• Issued: 09/02/2014
• Est. Priority Date: 06/25/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Moshayedi, Mark, Sadr, Seyed Jalal
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): DILLON, SAMUEL A
• Application Number:
  US12/492,113
• Publication Number:
  US 20090327591A1
• Time in Patent Office: 1,895 Days
• Field of Search: 711/103, 711/170, 711/173, 714/47.1, 714/47.2
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash.

Claims

1. A method of storing data in a flash storage device comprising non-volatile memory, the non-volatile memory comprising SLC and MLC flash memory, the method comprising the steps of:

checking an erase count associated with a first data block in the MLC flash memory;

moving data stored in the first data block to a second data block in the SLC flash memory when the erase count satisfies a first threshold; and

moving the data from the second data block in the SLC flash memory to a third data block in the MLC flash memory when a write count associated with the second data block satisfies a second threshold and a number of data blocks in the SLC flash memory storing data therein satisfies a third threshold, the third data block being associated with a write count lower than the write count associated with the second data block.

2. The method of claim 1, further comprising adding the erase count to a redundancy field of the first data block.

3. The method of claim 1, further comprising comparing a write count associated with a logical block address associated with the data to another predetermined threshold.

4. The method of claim 1, wherein the first threshold is 500.

5. The method of claim 1, wherein the first threshold is 1000.

6. The method of claim 1, further comprising creating a set of linked lists that track a number of valid segments in each data block of the non-volatile memory.

7. The method of claim 1, further comprising creating a set of linked lists that track a relative number of times data blocks of the non-volatile memory have been erased based on a lowest erase count among the data blocks.

8. The method of claim 1, further comprising creating a set of linked lists that track a number of faulty data blocks in the non-volatile memory.

9. A flash storage device comprising:

a volatile memory;

one or more channels of non-volatile flash memory including SLC flash memory and MLC flash memory; and

a controller configured to;

check an erase count associated with a first data block in the MLC flash memory;

move data stored in the first data block to a second data block in the SLC flash memory when the erase count satisfies a first threshold; and

move the data from the second data block in the SLC flash memory to a third data block in the MLC flash memory when a write count associated with the second data block satisfies a second threshold and a number of data blocks in the SLC flash memory storing data therein satisfies a third threshold, the third data block being associated with a write count lower than the write count associated with the second data block.

10. The flash storage device of claim 9, wherein the one or more channels of non-volatile flash memory each comprise a SLC chip and a plurality of MLC chips.

11. The flash storage device of claim 10, wherein each of the one or more channels comprise four MLC chips.

12. The flash storage device of claim 9, wherein the processor is further configured to add the erase count to a redundancy field of the first data block.

13. The flash storage device of claim 9, wherein the processor is further configured to compare a write count associated with a logical block address associated with the data to another predetermined threshold.

14. The flash storage device of claim 9, wherein the processor is further configured to compare the erase count to a predetermined threshold.

15. The flash storage device of claim 9, wherein moving the data is further based on a set of linked lists that track a number of valid segments in each data block of the non-volatile memory.

16. The flash storage device of claim 9, wherein moving the data is further based on a set of linked lists that track a relative number of times blocks have been erased based on the lowest erase count among the data blocks of the non-volatile memory.

17. The flash storage device of claim 9, wherein moving the data is further based on a set of linked lists that track a number of faulty blocks in each data block of the non-volatile memory.

18. The flash storage device of claim 9, wherein the controller further comprises a host I/F.

19. The flash storage device of claim 9, wherein the controller further comprises a sector buffer unit having a sector buffer for each channel of the non-volatile memory.

20. The flash storage device of claim 9, wherein the controller further comprises a virtual-to-physical (V2P) table RAM unit having a V2P table for each channel of the non-volatile memory.

21. A non-transitory machine-readable storage medium including one or more sequences of machine-readable instructions for storing data in a flash storage device including SLC flash memory and MLC flash memory, wherein execution of the one or more sequences by one or more processors causes the one or more processors to perform the steps of:

checking an erase count associated with a first data block in the MLC flash memory;

moving data stored in the first data block to a second data block in the SLC flash memory when the erase count satisfies a first threshold; and

moving the data from the second data block in the SLC flash memory to a third data block in the MLC flash memory when a write count associated with the second data block satisfies a second threshold and a number of data blocks in the SLC flash memory storing data therein satisfies a third threshold, the third data block being associated with a write count lower than the write count associated with the second data block.