Scan topology discovery in target systems

• US 8,826,088 B2
• Filed: 12/10/2013
• Issued: 09/02/2014
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US14/101,871
• Publication Number:
  US 20140101503A1
• Time in Patent Office: 266 Days
• Field of Search: 714/726, 714/727, 714/729
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Claims

1. A system comprising:

A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;

B. a first integrated circuit die having a die data in lead connected to the test data in lead, a die data out lead coupled to the test data out lead, a die clock lead connected to the test clock lead, and a die mode lead connected to the test mode select lead, the first integrated circuit die including topology selection logic coupled to the die data in lead, the die data out lead, the die clock lead and the die mode lead, the topology selection logic including a topology register containing bit positions indicating one of plural topologies in which the first integrated circuit die is connected.

2. The system of claim 1 including a second integrated circuit die having a die data in lead coupled to the die data out lead of the first integrated circuit die, a die data out lead connected to the test data out lead, a die clock lead connected to the test clock lead, and a die mode lead connected to the test mode select lead, the second integrated circuit die including topology selection logic coupled to the die data in lead, the die data out lead, the die clock lead and the die mode lead, the topology selection logic including a topology register containing bit positions indicating one of plural topologies in which the second integrated circuit die is connected.

3. The system of claim 1 including a second integrated circuit die having a die data in lead, a die data out lead, a die clock lead connected to the test clock lead, and a die mode lead connected to the test mode select lead, the second integrated circuit die including topology selection logic coupled to the die data in lead, the die data out lead, the die clock lead and the die mode lead, the topology selection logic including a topology register containing bit positions indicating one of plural topologies in which the second integrated circuit die is connected, and the second integrated circuit die being connected with the first integrated circuit die in a series scan topology.

4. The system of claim 1 in which the die data out lead is connected to the test data out lead through another integrated circuit die.

5. The system of claim 1 including a debug test system having a debug data in lead coupled to the test data in lead, a debug test data out lead coupled to the test data out lead, a debug clock lead coupled to the test clock lead, and a debug mode lead coupled to the test mode select lead.