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Automated inline defect characterization

  • US 8,826,209 B2
  • Filed: 06/29/2012
  • Issued: 09/02/2014
  • Est. Priority Date: 06/30/2011
  • Status: Active Grant
First Claim
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1. A computer implemented method for performing defect characterization comprising:

  • importing a layout for a semiconductor circuit;

    importing a netlist for the semiconductor circuit;

    obtaining images of a semiconductor chip which comprises the semiconductor circuit during fabrication;

    detecting, using one or more processors, a defect in one of the images of the semiconductor chip wherein the defect is at a location on a portion of the semiconductor chip that is represented by the layout and wherein the detecting is based on determining a critical volume; and

    performing an electrical analysis of the netlist with the detected defect.

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