Sensor manufacturing method

• US 8,828,771 B2
• Filed: 11/16/2012
• Issued: 09/09/2014
• Est. Priority Date: 11/18/2011
• Status: Active Grant

• Current Assignee: Chuan-Wei Wang
• Original Assignee: Chuan-Wei Wang
• Inventors: Wang, Chuan-Wei
• Primary Examiner(s): Picardat, Kevin M
• Assistant Examiner(s): Perkins, Pamela E
• Application Number:
  US13/679,322
• Publication Number:
  US 20130126990A1
• Time in Patent Office: 662 Days
• Field of Search: None
• US Class Current: 438/50
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H04R 19/005 using semiconductor materials
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 31/00 Apparatus or processes specially adapted for the manufacture of transducers or diaphragms therefor manufacture of microstructural arrangements of deformable or non-deformable structures in general B81C1/00182

Abstract

A sensor manufacturing method and a microphone structure produced by using the same. Wherein, thermal oxidation method is used to form a sacrifice layer of an insulation layer on a silicon-on-insulator (SOI) substrate or a silicon substrate, to fill patterned via in said substrate. Next, form a conduction wiring layer on the insulation layer. Since the conduction wiring layer is provided with holes, thus etching gas can be led in through said hole, to remove filling in the patterned via, to obtain an MEMS sensor. Or after etching of the conduction wiring layer, deep reactive-ion etching is used to etch the silicon substrate into patterned via, to connect the substrate electrically to a circuit chip. The manufacturing process is simple and the technology is stable and mature, thus the conduction wiring layer and the insulation layer are used to realize electrical isolation.

Claims

1. A sensor manufacturing method, comprising following steps:

provide a silicon-on-insulator (SOI) substrate, a silicon layer of said SOI substrate is penetrated with at least a trench;

form at least a patterned via through said silicon layer, and form at least a sacrifice layer on said silicon layer, to fill said trench and said patterned via;

remove part of said sacrifice layer, to expose said silicon layer, and form a first metal layer on said sacrifice layer, to connect it electrically to said silicon layer;

at a position corresponding to said patterned via, form at least an opening in said first metal layer, to expose said sacrifice layer, and form a first insulation layer to fill said opening; and

form a first insulation block on said first insulation layer, form a second insulation block and a metal block on said first metal layer, such that said first insulation block and said second insulation block are adjacent to said metal block, and are located respectively inside and outside said metal block to form a second metal layer having at least a hole with its position corresponding to that of said patterned via on said first insulation block, said second insulation block, and said metal block, and forma second insulation layer in said hole to be located on said first insulation block; and

through said hole, remove said sacrifice layer in said patterned via.

2. The sensor manufacturing method as claimed in claim 1, wherein in said step of forming said patterned via in said silicon layer, forming said sacrifice layer on said silicon layer, and filling said trench and said patterned via further includes following steps:

utilize thermal oxidation method or plasma enhanced chemical vapor deposition (PECVD) to form an oxidation layer on said silicon layer, to fill said trench;

remove part of said oxidation layer and said silicon layer below, to form said patterned via; and

fill a sacrifice structure in said patterned via, and form said sacrifice layer on said silicon layer.

3. The sensor manufacturing method as claimed in claim 1, wherein in said step of removing said sacrifice layer in said patterned via through said hole, remove in sequence said second insulation layer, said first insulation block, said first insulation layer, said sacrifice layer inside said first metal layer, said sacrifice layer in said patterned via, and a silicon oxide layer on said SOI substrate, wherein, said first insulation layer, said second insulation layer, said first insulation block, and said second insulation block are made of silicon dioxide.

4. The sensor manufacturing method as claimed in claim 1, wherein deep reactive-ion etching is used to form said patterned via, position of said hole corresponds to that of said trench, and

in said step of removing said sacrifice layer in said patterned via through said hole, remove at the same time said sacrifice layers in said trench and said patterned via;

and

in said step of removing said part of said sacrifice layer to expose said silicon layer, remove said part of said sacrifice layer to expose said silicon layer, such that said sacrifice layer has a first sacrifice block and a second sacrifice block, and said second sacrifice block is on an outer perimeter of said first sacrifice block, said first sacrifice layer is made of silicon dioxide, while said second sacrifice block is made of silicon dioxide, silicon carbide, or undoping polysilicon.

5. The sensor manufacturing method as claimed in claim 1, wherein

in said step of removing said sacrifice layer in said patterned via through said hole, use Hydrogen Fluoride (HF) vapor through said hole, or performing wet

etching through said hole;

and

after said step of removing said sacrifice layer in said patterned via through said hole, a step of forming at least an insulation layer on said second metal layer, to seal off said hole is performed.

6. The sensor manufacturing method as claimed in claim 1, wherein after said step of forming said conduction wiring layer on said sacrifice layer, to connect it electrically to said silicon layer, form an opening in said silicon layer of said SOI substrate, to expose a silicon dioxide layer of said SOI substrate, and position of said opening corresponds to that of said patterned via;

and

in said step of removing said sacrifice layer in said patterned via through said hole, remove said sacrifice layer in said patterned via through said hole, so that said opening connects with said patterned via.

7. A sensor manufacturing method, comprising following steps:

provide a silicon substrate, that is provided with at least a trench penetrating through said silicon substrate;

form a sacrifice layer on said silicon substrate, to fill said trench;

remove a part of said sacrifice layer, to expose said silicon substrate, and form a first metal layer on said sacrifice layer, to connect it electrically to said silicon substrate;

at a position corresponding to said sacrifice layer inside said first metal layer, form at least an opening in said first metal layer, to expose said sacrifice layer, and form a second insulation layer to fill said opening;

form a metal wiring layer having at least a hole on said first metal layer and said second insulation layer, and position of said hole corresponds to that of said sacrifice layer on an inner side of said first metal layer;

through said hole, remove said sacrifice layer on said inner side;

form in sequence a first insulation layer and a connection layer on said conduction wiring layer, to seal off said hole; and

at a position corresponding to said hole, form at least a patterned via penetrating through said silicon substrate.

8. The sensor manufacturing method as claimed in claim 7, wherein

in said step of forming said metal wiring layer on said first metal layer and said second insulation layer, form a first insulation block on said second insulation layer, form a second insulation block and a metal block on said first metal layer, said first insulation block and said second insulation block are adjacent to said metal block, and are located respectively inside and outside said metal block, form a second metal layer having said hole on said first insulation block, said second insulation block, and said metal block, and form a third insulation layer in said hole to be located on said first insulation block, so that said metal wiring layer is formed on said first metal layer and said second insulation layer;

in said step of removing said sacrifice layer inside said conduction wiring layer through said hole, remove said third insulation layer, said first insulation block, said second insulation layer, said sacrifice layer on inner side of said first metal layer; and

in said step of removing said part of said sacrifice layer to expose said silicon substrate, remove said part of said sacrifice layer to expose said silicon substrate, so that said sacrifice layer has a first sacrifice block and a second sacrifice block, and said second sacrifice block is on an outer perimeter of said first sacrifice block, such that said first sacrifice block is made of silicon dioxide, while said second sacrifice block is made of silicon dioxide, silicon carbide, or undoping polysilicon.

9. The sensor manufacturing method as claimed in claim 7, wherein said patterned via is formed through deep reactive-ion etching, and said sacrifice layer is formed by using thermal oxidation method or plasma enhanced chemical vapor deposition (PECVD), in said step of removing said sacrifice layer in said patterned via through said hole, use Hydrogen Fluoride (HF) vapor through said hole, or utilize wet etching through said hole;

and after said step of forming said pattern via in said silicon substrate, at least a circuit chip is fixed onto said silicon substrate by means of hermetic bonding.