Approach to integrate Schottky in MOSFET

• US 8,828,857 B2
• Filed: 04/29/2013
• Issued: 09/09/2014
• Est. Priority Date: 04/04/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik, Su, Yi, Ng, Daniel, Bhalla, Anup
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US13/873,017
• Publication Number:
  US 20140151790A1
• Time in Patent Office: 498 Days
• Field of Search: 257/155, 257/267, 257/284, 257/449, 257E29271-E29317, 438571-576
• US Class Current: 438/576
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

Claims

1. A method for forming an integrated structure combining one or more field effect transistors and a Schottky diode, the method comprising:

a) forming a plurality of trenches formed into a semiconductor substrate and extending into the substrate thereby forming a plurality of mesas there between, each trench being substantially filled with a conductive material that is separated from the trench walls by a thin layer of dielectric material to form a gate region of one or more field effect transistors;

b) forming at least two contact trenches in each mesa, each contact trench extending along a portion of depth of a doped body region of a first conductivity type opposite that of the substrate formed inside each mesa, whereby at least two contact trenches are separated by an exposed portion of the substrate, wherein each contact trench has an end that abuts the exposed portion of the substrate composition;

c) forming a pair of doped source regions of a second conductivity type formed adjacent to and on opposite sides of each contact trench inside the doped body region; and

d) forming a Schottky diode comprising Schottky barrier metal formed over the exposed portion of the substrate, the Schottky barrier metal forming a Schottky junction at an interface between the Schottky barrier metal and an exposed surface of the exposed portion of the substrate separating the two contact trenches.

2. The method of claim 1, further comprising forming a doped shielding region of the first conductivity type inside each doped body region, the doped shielding region extending along an entire depth of the doped body region and into a portion of the exposed vertical sidewall of the exposed portion of the substrate composition separating the two doped body regions.

3. The method of claim 2, wherein the doped shielding region is heavily doped.

4. The method of claim 2, wherein the substrate composition is a substrate.

5. The method of claim 2, wherein the substrate composition is a substrate with an epitaxial layer formed thereon.

6. The method of claim 5, wherein the portion of the substrate composition separating the two doped body regions is the epitaxial layer.

7. The method of claim 2, wherein the doped shielding region surrounds all bottom corners of the contact trench formed by the doped body region and extends into a bottom portion of the exposed vertical sidewall of the substrate.

8. The method of claim 7, further comprising forming an additional doped shielding region of the first conductivity type inside a top surface of the exposed portion of the substrate composition separating the two doped body regions.

9. The method of claim 2, wherein the doped shielding region extends along an entire width or length of sidewalls of the contact trench formed by the body regions, the doped shielding region also being formed within a portion of the exposed vertical sidewall of the substrate composition, the doped shielding region extending along an entire width or length of the exposed vertical sidewall.

10. The method of claim 2, wherein the first conductivity type is p type.

11. The method of claim 2, wherein the second conductivity type is n type.

12. The method of claim 2, wherein the Schottky diode and one or more MOSFET devices are integrated into different adjacent mesas.

13. A device, comprising:

a) a plurality of trenches formed into a semiconductor substrate and extending into the substrate forming a plurality of mesas there between, each trench being substantially filled with a conductive material that is separated from the trench walls by a thin layer of dielectric material to form a gate region of one or more field effect transistors;

b) at least two contact trenches formed in each mesa, each contact trench extending along a portion of depth of a doped body region of a first conductivity type opposite that of the substrate formed inside each mesa, whereby at least two contact trenches are separated by an exposed portion of the substrate, wherein each contact trench has an end that abuts the exposed portion of the substrate composition;

c) a pair of doped source regions of a second conductivity type formed adjacent to and on opposite sides of each contact trench inside the doped body region; and

d) a Schottky diode comprising Schottky barrier metal formed over the exposed portion of the substrate, the Schottky barrier metal forming a Schottky junction at an interface between the Schottky barrier metal and an exposed surface of the exposed portion of the substrate separating the two contact trenches.

14. The device of claim 13, wherein the Schottky barrier metal is formed within each contact trench and along each exposed vertical sidewall at the ends of the contact trench.

15. The device of claim 13, wherein the first conductivity type is p type.

16. The device of claim 13, wherein the second conductivity type is n type.

17. The device of claim 13, wherein the Schottky diode and one or more MOSFET devices are integrated into different adjacent mesas.

18. The device of claim 13, wherein the doped body regions are separated by the exposed portion of the substrate.

19. The device of claim 18, wherein the substrate includes an epitaxial layer formed thereon.

20. The device of claim 19, wherein the portion of the substrate separating the two doped body regions is the epitaxial layer.