Nitride semiconductor template and light-emitting diode

• US 8,829,489 B2
• Filed: 12/13/2012
• Issued: 09/09/2014
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Sumitomo Chemical Company Limited
• Original Assignee: Hitachi Metals (Thailand) Ltd.
• Inventors: Konno, Taichiroo, Fujikura, Hajime
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US13/714,300
• Publication Number:
  US 20130153858A1
• Time in Patent Office: 635 Days
• Field of Search: 257/13
• US Class Current: 257/13
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/325 characterised by the doping materials

Abstract

A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×10¹⁷ cm⁻³ and not more than 5×10¹⁷ cm⁻³ at the outermost surface of the group III nitride semiconductor layer.

Claims

1. A nitride semiconductor template, comprising:

a substrate; and

a group III nitride semiconductor layer formed on the substrate and comprising a Si-doped layer doped with Si as an uppermost layer thereof,

wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μ

m and not more than 10 μ

m, and

wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×

10¹⁷ cm<sup>−

3</sup> and not more than 5×

10¹⁷ cm<sup>−

3</sup> at the outermost surface of the group III nitride semiconductor layer.

2. The nitride semiconductor template according to claim 1, wherein the group III nitride semiconductor layer comprises an O-doped layer doped with O (oxygen) between the substrate and the Si-doped layer.

3. The nitride semiconductor template according to claim 2, wherein the O-doped layer has an O-impurity concentration of not less than 1×

10¹⁶ cm<sup>−

3</sup> and not more than 3×

10¹⁹ cm<sup>−

3</sup> and an average carrier concentration in a thickness direction of not less than 8×

10¹⁷ cm<sup>−

3</sup> and not more than 1×

10¹⁸ cm<sup>−

3</sup>.

4. The nitride semiconductor template according to claim 1, wherein the Si-doped layer comprises a high Si concentration layer having a uniform carrier concentration in a thickness direction, and

wherein the Si concentration gradient layer has a carrier concentration that gradually decreases from the high Si concentration layer toward the outermost surface.

5. The nitride semiconductor template according to claim 4, wherein the carrier concentration of the high Si concentration layer is not less than 1×

10¹⁷ cm<sup>−

3</sup> and not more than 1×

10¹⁹ cm<sup>−

3</sup>.

6. The nitride semiconductor template according to claim 1, wherein the substrate comprises a PSS (Patterned Sapphire Substrate) comprising a plurality of convex portions on a surface thereof.

7. The nitride semiconductor template according to claim 1, wherein the template has a surface resistivity of not less than 10 Ω

/sq and not more than 30 Ω

/sq.

8. The nitride semiconductor template according to claim 1, wherein the template has a half-value width at a (0004) plane of not more than 100 seconds by X-ray diffraction measurement.

9. A light-emitting diode, comprising:

a sapphire substrate;

an AlN buffer layer formed on the sapphire substrate;

an n-type group III nitride semiconductor layer formed on the AlN buffer layer;

a multiple quantum well layer formed on the n-type group III nitride semiconductor layer;

a p-type nitride semiconductor layer formed on the multiple quantum well layer;

an exposed portion of the n-type group III nitride semiconductor layer formed by etching from the p-type nitride semiconductor layer to the n-type group III nitride semiconductor layer;

an n-type electrode formed on the exposed portion of the n-type group III nitride semiconductor layer; and

a p-type electrode formed on the p-type nitride semiconductor layer,

wherein the n-type group III nitride semiconductor layer comprises a group III nitride semiconductor layer comprising a Si-doped layer doped with Si as an uppermost layer thereof,

wherein the group III nitride semiconductor layer has a total thickness of not less than 4 μ

m and not more than 10 μ

m, and

wherein the Si-doped layer comprises a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×

10¹⁷ cm<sup>−

3</sup> and not more than 5×

10¹⁷ cm<sup>−

3</sup> at the outermost surface of the group III nitride semiconductor layer.