Semiconductor device including a dielectric structure in a trench

• US 8,829,562 B2
• Filed: 07/24/2012
• Issued: 09/09/2014
• Est. Priority Date: 07/24/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schulze, Hans-Joachim, Hirler, Franz, Felsl, Hans-Peter, Niedernostheide, Franz-Josef
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): Tran, Dzung
• Application Number:
  US13/556,335
• Publication Number:
  US 20140027812A1
• Time in Patent Office: 777 Days
• Field of Search: 257/139, 257/328, 257/330, 257/332, 438/268, 438/259
• US Class Current: 257/139
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a trench extending into a drift zone of a semiconductor body from a first surface. The semiconductor device further includes a gate electrode in the trench and a body region adjoining a sidewall of the trench. The semiconductor device further includes a dielectric structure in the trench. The dielectric structure includes a high-k dielectric in a lower part of the trench. The high-k dielectric includes a dielectric constant higher than that of SiO₂. An extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.

Claims

1. A semiconductor device, comprising:

a trench extending into a drift zone of a semiconductor body from a first surface;

a gate electrode in the trench;

a body region adjoining a sidewall of the trench;

a dielectric structure in the trench, the dielectric structure directly adjoining the semiconductor body along the bottom of the trench, and the dielectric structure including a high-k dielectric in a lower part of the trench, wherein the high-k dielectric includes a dielectric constant higher than that of SiO₂; and

wherein an extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench; and

wherein the high-k dielectric is spaced from the bottom side of the trench along the vertical direction by a portion of the dielectric structure including a first dielectric layer.

2. The semiconductor device of claim 1, wherein the high-k dielectric includes at least one of Al₂O₃, Ta₂O₅, and ZrO₂.

3. The semiconductor device of claim 1, wherein a thickness of the dielectric ranges between 50 nm and 1 μ

m.

4. The semiconductor device of claim 1, further comprising a field electrode in the trench below the gate electrode.

5. The semiconductor device of claim 1, wherein the high-k dielectric lines opposing sidewalls and a bottom side of the trench.

6. The semiconductor device of claim 1, wherein the high-k dielectric is sandwiched between the first dielectric layer and a second dielectric layer.

7. The semiconductor device of claim 1, wherein the first dielectric is between the high-k dielectric and the semiconductor body.

8. The semiconductor device of claim 7, wherein the first dielectric includes SiO₂.

9. The semiconductor device of claim 1, wherein the dielectric structure further includes a charged dielectric in a lower part of the trench, wherein a surface charge of the charged dielectric ranges between 10¹¹ cm⁻

2 and 10¹³ cm<sup>−

2</sup>; and

wherein an extension of the charged dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.

10. The semiconductor device of claim 9, wherein the charged dielectric adjoins the high-k dielectric.

11. The semiconductor device of claim 9, wherein an intermediate dielectric is between the high-k dielectric and the charged dielectric.

12. The semiconductor device of claim 9, wherein the charged dielectric includes a negative charge.

13. The semiconductor device of claim 12, wherein the charged dielectric includes cesium.

14. The semiconductor device of claim 1, wherein the semiconductor device is an Insulated Gate Bipolar Transistor.

15. The semiconductor device of claim 1, wherein the semiconductor device is a Field Effect Transistor.

16. The semiconductor device of claim 1, wherein the extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between the bottom side of the trench and a level between 10% to 50% of a distance from the bottom side of the trench to the level where the bottom side of the body region adjoins the sidewall of the trench.

17. A semiconductor device, comprising:

a trench extending into a drift zone of a semiconductor body from a first surface;

a gate electrode in the trench;

a body region adjoining a sidewall of the trench;

a dielectric structure in the trench, the dielectric structure including a charged dielectric in a lower part of the trench, wherein a net charge of the dielectric corresponds to a surface charge of the charged dielectric ranging between 10¹¹ cm<sup>−

2</sup> and 10¹³ cm<sup>−

2</sup>; and

wherein an extension of the charged dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.

18. The semiconductor device of claim 17, wherein the charged dielectric lines opposing sidewalls and the bottom side of the trench.

19. The semiconductor device of claim 17 wherein the charged dielectric includes a negative charge.

20. The semiconductor device of claim 19, wherein the charged dielectric includes cesium.

21. The semiconductor device of claim 17, wherein the charged dielectric is sandwiched between a first dielectric layer and a second dielectric layer.

22. The semiconductor device of claim 17, wherein a first dielectric is between the charged dielectric and the semiconductor body.

23. The semiconductor device of claim 17, wherein the dielectric structure further includes a high-k dielectric in a lower part of the trench, wherein the high-k dielectric includes a dielectric constant higher than that of SiO₂;

and wherein an extension of the high-k dielectric in a vertical direction perpendicular to the first surface is limited between a bottom side of the trench and a level where a bottom side of the body region adjoins the sidewall of the trench.

24. The semiconductor device of claim 23, wherein the charged dielectric adjoins the high-k dielectric.

25. The semiconductor device of claim 23, wherein an intermediate dielectric is between the high-k dielectric and the charged dielectric.

26. The semiconductor device of claim 17, wherein the extension of the charged dielectric in a vertical direction perpendicular to the first surface is limited between the bottom side of the trench and a level between 10% to 50% of a distance from the bottom side of the trench to the level where the bottom side of the body region adjoins the sidewall of the trench.