Semiconductor device including an IGBT

• US 8,829,564 B2
• Filed: 07/08/2013
• Issued: 09/09/2014
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Nakamura, Katsumi
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/936,608
• Publication Number:
  US 20130292738A1
• Time in Patent Office: 428 Days
• Field of Search: 257/330, 257/146
• US Class Current: 257/146
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes a semiconductor substrate and a MOS transistor. The semiconductor substrate has the first main surface and the second main surface facing each other. The MOS transistor includes a gate electrode (5a) formed on the first main surface side, an emitter electrode (11) formed on the first main surface side, and a collector electrode (12) formed in contact with the second main surface. An element generates an electric field in a channel by a voltage applied to the gate electrode (5a), and controls the current between the emitter electrode (11) and the collector electrode (12) by the electric field in the channel. The spike density in the interface between the semiconductor substrate and the collector electrode (12) is not less than 0 and not more than 3×10⁸ unit/cm². Consequently, a semiconductor device suitable for parallel operation is provided.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other; and

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel, wherein

said second main surface has a center line average roughness of greater than 0 and not more than 200 nm.

2. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other; and

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel, wherein said second main surface has a maximum height of greater than 0 and not more than 2000 nm.

3. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other; and

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel, wherein

a gate groove is formed in said first main surface of said semiconductor substrate, and said gate groove is filled with said gate electrode,

a plurality of grooves are formed in said first main surface of said semiconductor substrate and said gate groove is at least one of said plurality of grooves, and

a ratio of a depth from said first main surface to a bottom of said gate groove to a pitch between said gate groove and another groove adjacent thereto is not less than 1.0.

4. A semiconductor device, comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other; and

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel, wherein

a gate groove is formed in said first main surface of said semiconductor substrate, and said gate groove is filled with said gate electrode,

a plurality of grooves are formed in said first main surface of said semiconductor substrate and said gate groove is at least one of said plurality of grooves,

a ratio of a depth from said first main surface to a bottom of said gate groove to a pitch between said gate groove and another groove adjacent thereto is not less than 1.0,

a plurality of grooves are formed in said first main surface of said semiconductor substrate, said plurality of grooves are arranged in one direction as seen in plan view, and said gate groove is at least one of said plurality of grooves,

said semiconductor device further comprises a well layer of a first conductivity type formed on said first main surface adjacent to each of said plurality of grooves, extending in said one direction as seen in plan view and formed deeper than each of said plurality of grooves, and

a depth from a bottom surface of said gate groove to a bottom of said well layer is greater than 0 and not more than 1.0 μ

m.

5. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel;

a collector region formed on said second main surface;

said collector region including a collector diffusion layer of a first conductivity type in contact with said second electrode, a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, and a drift diffusion layer of the second conductivity type, and said drift diffusion layer being lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is;

a body diffusion layer of the first conductivity type serving as said channel; and

a buried diffusion layer of the second conductivity type formed between said body diffusion layer and said drift diffusion layer.

6. The semiconductor device according to claim 5, wherein a groove is formed in said first main surface of said semiconductor substrate, and said groove protrudes toward the second main surface with respect to a position where the impurity concentration in said buried diffusion layer is 1×

10¹⁶cm<sup>−

3</sup>.

7. The semiconductor device according to claim 5, wherein

a gate groove and an emitter groove are formed in said first main surface of said semiconductor substrate, said gate groove is filled with said gate electrode, and said emitter groove is filled with a conductive layer having an emitter potential, and

said buried diffusion layer is formed so as to be brought into contact with said emitter groove but not with the gate groove.

8. The semiconductor device according to claim 7, wherein said buried diffusion layer has a width of not less than 6.0 μ

m and not more than 9 μ

m as seen in plan view in a region existing around said emitter groove.

9. The semiconductor device according to claim 7, wherein a distance from said emitter groove to an end of said buried diffusion layer is not less than 0.5 μ

m and not more than 2 μ

m.

10. The semiconductor device according to claim 5, wherein

a gate groove and an emitter groove are formed in said first main surface of said semiconductor substrate, said gate groove is filled with said gate electrode, and said emitter groove is filled with a conductive layer having an emitter potential, and

said buried diffusion layer is formed so as to be brought into contact with said gate groove but not with the emitter groove.

11. The semiconductor device according to claim 5, wherein

a plurality of grooves are formed in said first main surface of said semiconductor substrate, and said plurality of grooves are arranged in one direction as seen in plan view, and

said buried diffusion layer is formed only in a region interposed between said grooves as seen in plan view.

12. The semiconductor device according to claim 11, further comprising a well layer of the first conductivity type formed on said first main surface adjacent to said plurality of grooves in a direction in which said plurality of grooves are arranged, extending in said one direction as seen in plan view and formed deeper than each of said plurality of grooves, wherein

said well layer is formed deeper than said buried diffusion layer.

13. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel;

a first emitter diffusion layer of a first conductivity type formed on said first main surface and in contact with said first electrode; and

a second emitter diffusion layer of a second conductivity type formed on said first main surface and in contact with said first electrode and said first emitter diffusion layer, wherein

a ratio of a width of said second emitter diffusion layer along a direction in which said gate electrode extends to a sum of said width of the first emitter diffusion layer and a width of the second emitter diffusion layer along the direction in which said gate electrode extends is not less than 0.08 and not more than 0.20.

14. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other; and

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel, wherein

an electric signal is transmitted to said gate electrode through a resistor body having a locally high electrical resistance value.

15. The semiconductor device according to claim 14, wherein said resistor body is identical in structure to said gate electrode.

16. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel;

a collector region formed on said second main surface; and

a body diffusion layer of a first conductivity type being in contact with said collector region and serving as said channel, wherein

said collector region includes a drift diffusion layer of a second conductivity type, and

an electric field intensity in a junction plane between said drift diffusion layer and said body diffusion layer obtained when a reverse voltage is applied to said element is greater than 0 and not more than 3.0×

10⁵ V/cm.

17. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel;

a collector region formed on said second main surface; and

a body diffusion layer of a first conductivity type being in contact with said collector region and serving as said channel, wherein

said collector region includes a collector diffusion layer of the first conductivity type in contact with said second electrode, a buffer diffusion layer of a second conductivity type formed closer to the first main surface than said collector diffusion layer is, and a drift diffusion layer of the second conductivity type, and said drift diffusion layer is lower in impurity concentration than said buffer diffusion layer and formed adjacent to said buffer diffusion layer and closer to the first main surface than said buffer diffusion layer is, and

an electric field intensity in a junction plane between said buffer diffusion layer and said drift diffusion layer obtained when a reverse voltage is applied to said element is not less than 2.0×

10⁴ V/cm and not more than an electric field intensity in a junction plane between said drift diffusion layer and said body diffusion layer.

18. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface, facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel; and

a body diffusion layer of a first conductivity type serving as said channel, wherein

a gate groove is formed in said first main surface of said semiconductor substrate, and said gate groove is filled with said gate electrode, and

a protrusion amount of said gate groove from a bottom of said body diffusion layer is not less than 1.0 μ

m and not more than a depth reaching said second main surface.

19. A semiconductor device comprising:

a semiconductor substrate having a first main surface and a second main surface facing each other;

an element having a gate electrode formed on a side of said first main surface, a first electrode formed on the side of said first main surface and a second electrode formed in contact with said second main surface, said element generating an electric field in a channel by a voltage applied to said gate electrode, and controlling a current between said first electrode and said second electrode by the electric field in said channel;

a body diffusion layer of a first conductivity type serving as said channel; and

a buried diffusion layer of a second conductivity type formed adjacent to a side surface of said body diffusion layer as seen in plan view; and

the semiconductor device is an IGBT of planar gate type.

20. The semiconductor device according to claim 19, further comprising a collector region formed on said second main surface, wherein

said collector region includes a drift diffusion layer of the first conductivity type adjacent to said buried diffusion layer and said body diffusion layer, and

a ratio of the number of atoms per unit area of impurities forming said buried diffusion layer to the number of atoms per unit area of impurities forming said drift diffusion layer is not less than 0 and not more than 20.