Integrated circuits and transistor design therefor
First Claim
1. An integrated circuit structure, comprising:
- a source region formed at a top portion of a first pillar;
a drain region formed at a top portion of a second pillar, each of the first and second pillars having inner surfaces that face each other and outer surfaces that do not face each other, and side walls that extend between respective inner and outer surfaces;
a connecting portion of semiconductor material that connects bottom portions of the first and second pillars, the connecting portion extending along a first axis between the first and second pillars;
a gate material extending parallel to the first axis, the gate material facing side walls of the first and second pillars;
a channel connecting the source region and the drain region, the channel formed adjacent the gate material in the connecting portion of semiconductor material and in the bottom portions of the first and second pillars;
a first trench adjacent to the outer surface of the first pillar, the first trench extending deeper into the semiconductor material than the connecting portion; and
a second trench adjacent to the outer surface of the second pillar, the second trench extending deeper into the semiconductor material than the connecting portion,wherein the first and second trenches are each filled with insulating material to isolate the integrated circuit structure from adjacent devices.
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Accused Products
Abstract
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
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Citations
26 Claims
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1. An integrated circuit structure, comprising:
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a source region formed at a top portion of a first pillar; a drain region formed at a top portion of a second pillar, each of the first and second pillars having inner surfaces that face each other and outer surfaces that do not face each other, and side walls that extend between respective inner and outer surfaces; a connecting portion of semiconductor material that connects bottom portions of the first and second pillars, the connecting portion extending along a first axis between the first and second pillars; a gate material extending parallel to the first axis, the gate material facing side walls of the first and second pillars; a channel connecting the source region and the drain region, the channel formed adjacent the gate material in the connecting portion of semiconductor material and in the bottom portions of the first and second pillars; a first trench adjacent to the outer surface of the first pillar, the first trench extending deeper into the semiconductor material than the connecting portion; and a second trench adjacent to the outer surface of the second pillar, the second trench extending deeper into the semiconductor material than the connecting portion, wherein the first and second trenches are each filled with insulating material to isolate the integrated circuit structure from adjacent devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit transistor comprising:
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a semiconductor structure including a pair of pillars and a connecting portion therebetween, the pillars having inner surfaces that face each other, outer surfaces opposite the inner surfaces, and side surfaces extending between respective inner and outer surfaces, wherein one of the pillars comprises a source region and the other of the pillars comprises a drain region; a dielectric material formed over at least a portion of the semiconductor structure; a channel extending between and forming an electrical connection between the pair of pillars, the channel including a portion extending along a first axis between the pillars; a gate material formed on the dielectric material and extending along side surfaces of the pillars elongated in a direction parallel to the first axis; a first trench adjacent to the outer surface of one of the pillars, the first trench extending deeper into the semiconductor material than the connecting portion; and a second trench adjacent to the outer surface of other of the pillars, the second trench extending deeper into the semiconductor material than the channel, wherein the first and second trenches are each filled with insulating material to isolate the integrated circuit transistor from adjacent devices. - View Dependent Claims (14, 15, 16, 17)
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18. An electronic device comprising:
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a semiconductor substrate that includes a first pillar and a second pillar, wherein a source region is formed at a top portion of the first pillar, and a drain region is formed at a top portion of the second pillar; a channel that is formed between the two pillars, and that provides an electrical connection between the source region and the drain region, the channel including a portion extending along a first axis between the two pillars; a gate dielectric layer positioned over at least a portion of the substrate and extending at least along a selected side wall of the first pillar and a selected side wall of the second pillar, wherein the selected side wall of the second pillar is parallel and aligned with the selected side wall of the first pillar, and wherein the selected side walls are parallel to the first axis; a gate material formed on the dielectric layer, the gate material extending at least along the selected side wall of the first pillar and the selected side wall of the second pillar; a first trench adjacent to an outer surface of the first pillar that is opposite the second pillar, the first trench extending deeper into the semiconductor material than the channel; and a second trench adjacent to an outer surface of the second pillar that is opposite to the first pillar, the second trench extending deeper into the semiconductor material than the channel, wherein the first and second trenches are each filled with insulating material to isolate the electronic device from adjacent devices. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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Specification