Integrated circuits and transistor design therefor

• US 8,829,602 B2
• Filed: 03/22/2011
• Issued: 09/09/2014
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Kalam, Abul
• Application Number:
  US13/053,604
• Publication Number:
  US 20110169063A1
• Time in Patent Office: 1,267 Days
• Field of Search: None
• US Class Current: 257/330
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Claims

1. An integrated circuit structure, comprising:

a source region formed at a top portion of a first pillar;

a drain region formed at a top portion of a second pillar, each of the first and second pillars having inner surfaces that face each other and outer surfaces that do not face each other, and side walls that extend between respective inner and outer surfaces;

a connecting portion of semiconductor material that connects bottom portions of the first and second pillars, the connecting portion extending along a first axis between the first and second pillars;

a gate material extending parallel to the first axis, the gate material facing side walls of the first and second pillars;

a channel connecting the source region and the drain region, the channel formed adjacent the gate material in the connecting portion of semiconductor material and in the bottom portions of the first and second pillars;

a first trench adjacent to the outer surface of the first pillar, the first trench extending deeper into the semiconductor material than the connecting portion; and

a second trench adjacent to the outer surface of the second pillar, the second trench extending deeper into the semiconductor material than the connecting portion,

wherein the first and second trenches are each filled with insulating material to isolate the integrated circuit structure from adjacent devices.

2. The integrated circuit of claim 1, wherein the gate material further comprises a portion interposed between the first and second pillars.

3. The integrated circuit of claim 1, wherein the channel is at least partially formed on an upper surface of the connecting portion of semiconductor material.

4. The integrated circuit of claim 1, wherein the first and second pillars comprise epitaxially formed silicon.

5. The integrated circuit of claim 1, wherein the gate material surrounds the bottom portions of the first and second pillars.

6. The integrated circuit of claim 1, further comprising a dielectric material positioned between the channel and the gate material.

7. The integrated circuit of claim 1, wherein the connecting portion of semiconductor material forms a portion of a bulk substrate.

8. The integrated circuit of claim 1, wherein the gate material comprises a material selected from the group consisting of metal, metal alloys and conductively-doped silicon.

9. The integrated circuit of claim 1, further comprising a memory storage device connected to the drain region.

10. The integrated circuit of claim 9, wherein the memory storage device comprises a capacitor.

11. The integrated circuit of claim 1, further comprising a digit line connected to the source region.

12. The integrated circuit of claim 11, further comprising a processor in communication with the digit line.

13. An integrated circuit transistor comprising:

a semiconductor structure including a pair of pillars and a connecting portion therebetween, the pillars having inner surfaces that face each other, outer surfaces opposite the inner surfaces, and side surfaces extending between respective inner and outer surfaces, wherein one of the pillars comprises a source region and the other of the pillars comprises a drain region;

a dielectric material formed over at least a portion of the semiconductor structure;

a channel extending between and forming an electrical connection between the pair of pillars, the channel including a portion extending along a first axis between the pillars;

a gate material formed on the dielectric material and extending along side surfaces of the pillars elongated in a direction parallel to the first axis;

a first trench adjacent to the outer surface of one of the pillars, the first trench extending deeper into the semiconductor material than the connecting portion; and

a second trench adjacent to the outer surface of other of the pillars, the second trench extending deeper into the semiconductor material than the channel,

wherein the first and second trenches are each filled with insulating material to isolate the integrated circuit transistor from adjacent devices.

14. The integrated circuit transistor of claim 13, wherein the gate material additionally includes a portion interposed between the pillars.

15. The integrated circuit transistor of claim 13, wherein the pillars comprise an epitaxial semiconductor material.

16. The integrated circuit transistor of claim 13, wherein the gate material comprises a material selected from the group consisting of metal, metal alloys and conductively-doped silicon.

17. The integrated circuit transistor of claim 13, wherein the gate material is positioned adjacent to opposite side surfaces of the pair of pillars.

18. An electronic device comprising:

a semiconductor substrate that includes a first pillar and a second pillar, wherein a source region is formed at a top portion of the first pillar, and a drain region is formed at a top portion of the second pillar;

a channel that is formed between the two pillars, and that provides an electrical connection between the source region and the drain region, the channel including a portion extending along a first axis between the two pillars;

a gate dielectric layer positioned over at least a portion of the substrate and extending at least along a selected side wall of the first pillar and a selected side wall of the second pillar, wherein the selected side wall of the second pillar is parallel and aligned with the selected side wall of the first pillar, and wherein the selected side walls are parallel to the first axis;

a gate material formed on the dielectric layer, the gate material extending at least along the selected side wall of the first pillar and the selected side wall of the second pillar;

a first trench adjacent to an outer surface of the first pillar that is opposite the second pillar, the first trench extending deeper into the semiconductor material than the channel; and

a second trench adjacent to an outer surface of the second pillar that is opposite to the first pillar, the second trench extending deeper into the semiconductor material than the channel,

wherein the first and second trenches are each filled with insulating material to isolate the electronic device from adjacent devices.

19. The electronic device of claim 18, wherein the channel is at least partially formed on an upper surface of a connecting portion of the semiconductor substrate that is located between the first pillar and the second pillar.

20. The electronic device of claim 18, wherein the pillars comprise epitaxial silicon.

21. The electronic device of claim 18, wherein the dielectric layer comprises an oxide material.

22. The electronic device of claim 18, further comprising:

a memory storage device electronically connected to the drain region; and

a digit line electronically connected to the source region.

23. The electronic device of claim 22, wherein the memory storage device and the gate dielectric layer form a portion of a DRAM cell.

24. The electronic device of claim 18, wherein the top portion of the first pillar is doped to a first conductivity type, and wherein a bottom portion of the first pillar is doped to a second conductivity type that is different from the first conductivity type.

25. The electronic device of claim 24, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

26. The electronic device of claim 24, wherein the first conductivity type is p-type, and the second conductivity type is n-type.