Semiconductor device having deep and shallow trenches

• US 8,829,605 B2
• Filed: 11/19/2012
• Issued: 09/09/2014
• Est. Priority Date: 12/20/2011
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Masuda, Takeyoshi, Wada, Keiji, Hiyoshi, Toru, Matsukawa, Shinji
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/680,798
• Publication Number:
  US 20130153926A1
• Time in Patent Office: 659 Days
• Field of Search: 257/77, 257329-334, 257/E29.257, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A MOSFET includes: a substrate made of silicon carbide and having a first trench and a second trench formed therein, the first trench having an opening at the main surface side, the second trench having an opening at the main surface side and being shallower than the first trench; a gate insulating film; a gate electrode; and a source electrode disposed on and in contact with a wall surface of the second trench. The substrate includes a source region, a body region, and a drift region. The first trench is formed to extend through the source region and the body region and reach the drift region. The second trench is formed to extend through the source region and reach the body region.

Claims

1. A semiconductor device comprising:

a substrate made of silicon carbide and having a first trench and a second trench formed therein, said first trench having an opening at a side of one main surface, said second trench having an opening at the side of said main surface and being shallower than said first trench;

a gate insulating film disposed on and in contact with a wall surface of said first trench;

a gate electrode disposed on and in contact with said gate insulating film; and

a contact electrode disposed on and in contact with a wall surface of said second trench,

said substrate including

a source region including said main surface of said substrate and said wall surface of said first trench,

a body region making contact with said source region and including said wall surface of said first trench, and

a drift region making contact with said body region and including said wall surface of said first trench,

said first trench being formed to extend through said source region and said body region and reach said drift region,

said second trench being formed to extend through said source region and reach said body region.

2. The semiconductor device according to claim 1, wherein said contact electrode is disposed not to be on and in contact with said main surface of said substrate.

3. The semiconductor device according to claim 1, wherein said wall surface of said second trench is constituted of a plane crossing a {0001} plane.

4. The semiconductor device according to claim 1, wherein in a cross section in a thickness direction of said substrate including said first and second trenches, a fictitious straight line (A-A) extending from said wall surface at a lowermost portion of said second trench in parallel with a {0001} plane crosses said wall surface of said first trench facing said second trench.

5. The semiconductor device according to claim 4, wherein in the cross section in the thickness direction of said substrate including said first and second trenches, said fictitious straight line (A-A) crosses said wall surface of said first trench facing said second trench, without crossing said drift region.

6. The semiconductor device according to claim 1, wherein said main surface of said substrate is constituted of a plane having an off angle of 8°

or smaller relative to a {0001} plane.

7. The semiconductor device according to claim 1, wherein said wall surface of said first trench forms an obtuse angle relative to said main surface of said substrate.

8. The semiconductor device according to claim 1, wherein said wall surface of said first trench is constituted of a plane having an off angle of not less than 50°

and not more than 65°

relative to a {0001} plane.

9. The semiconductor device according to claim 1, wherein said body region has an impurity concentration of not less than 1.0×

10¹⁷ cm<sup>−

3</sup> and not more than 5.0×

10¹⁸ cm<sup>−

3</sup>.