Fast switching super-junction trench MOSFETs

• US 8,829,607 B1
• Filed: 07/25/2013
• Issued: 09/09/2014
• Est. Priority Date: 07/25/2013
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd., Fu-Yuan Hsieh
• Original Assignee: Force Mos Technology Co., Ltd., Fu-Yuan Hsieh
• Inventors: Hsieh, Fu-Yuan
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/950,692
• Time in Patent Office: 411 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/334, 257/E29.257, 257/E21.384, 257/E29.262, 257/E21.41
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fast switching super-junction trench MOSFET is disclosed having a floating region formed underneath each gate trench and surrounding at least bottom of each the gate trench, which has a parasitic body diode with superior reverse recovery characteristics.

Claims

1. A super-junction trench MOSFET comprising a plurality of unit cells with each unit cell in an active area comprising:

a substrate of a first conductivity type;

an epitaxial layer of said first conductivity type grown on said substrate, said epitaxial layer having a lower doping concentration than said substrate;

a pair of deep trenches starting from a top surface of said epitaxial layer and down extending into said epitaxial layer;

a mesa between said pair of deep trenches;

a first doped column region of said first conductivity type with column shape within each said mesa;

a body region of a second conductivity type in said mesa, covering a top surface of said first doped column region, extending between said pair of deep trenches;

at least one gate trench filled with a gate electrode padded by a gate oxide layer, starting from the top surface of said epitaxial layer and down penetrating through said body region and extending into said first doped column in said mesa;

multiple source-body contact openings with each filled with a contact metal plug extending into said body region in said mesa;

a source region of said first conductivity type surrounding an upper portion of each said gate trench, extending between the upper portion of each said gate trench and sidewalls of adjacent source-body contact openings; and

a floating region of said second conductivity type formed underneath each said gate trench and surrounding at least bottom of each said gate trench.

2. The super-junction trench MOSFET of claim 1 further comprising a pair of second doped column regions of said second conductivity type with column shape adjacent to sidewalls of said pair of deep trenches within said mesa, in parallel with and surrounding said first doped column region forming a first type charge balance area in conjunction with said first doped column region, wherein each of said deep trenches is filled with dielectric material comprising a buried void inside said dielectric material.

3. The super-junction trench MOSFET of claim 1 further comprising a pair of second doped column regions of said second conductivity type with column shape adjacent to sidewalls of said pair of deep trenches within said mesa, in parallel with and surrounding said first doped column region forming a first type charge balance area in conjunction with said first doped column region, wherein each of said deep trenches is filled with dielectric material without a buried void inside said dielectric material.

4. The super-junction trench MOSFET of claim 1 further comprising a pair of second doped column regions of said second conductivity type with column shape adjacent to sidewalls of said pair of deep trenches within said mesa, in parallel with and surrounding said first doped column region forming a first type charge balance area in conjunction with said first doped column region, wherein each of said deep trenches is filled with a shield electrode padded by a dielectric material layer, said shield electrode is connecting to a source metal of said super-junction trench MOSFET via the contact metal plug filled in each shield contact opening.

5. The super-junction trench MOSFET of claim 1, wherein each of said deep trenches is filled with an epitaxial layer of said second conductivity type working as second doped column regions, said pair of deep trenches in parallel with and surrounding said first doped column region forming a first type charge balance area in conjunction with said first doped column region.

6. The super-junction trench MOSFET of claim 1, wherein said deep trenches further extend into said substrate, and said first doped column region reach a common interface between said substrate and said epitaxial layer.

7. The super junction trench MOSFET of claim 1, wherein trench bottoms of said deep trenches are above said substrate.

8. The super-junction trench MOSFET of claim 1 further comprising a body contact region of said second conductivity type within said body region and surrounding at least bottom of each said multiple source-body contact openings, wherein said body contact region has a higher doping concentration than said body region.

9. The super-junction trench MOSFET of claim 1, wherein said contact metal plug is a tungsten plug padded by a barrier metal layer of Ti/TiN or Co/TiN or Ta/TiN.

10. The super junction trench MOSFET of claim 1, wherein said gate electrode is connected to a gate metal via a gate contact opening filled with said contact metal plug.

11. The super junction trench MOSFET of claim 1, wherein said gate electrode is implemented by a poly-silicon layer.

12. The super-junction trench MOSFET of claim 1, wherein said gate oxide layer has a thickness on trench bottom equal to or thinner than trench sidewalls of said gate trench.

13. The super-junction trench MOSFET of claim 1, wherein said gate oxide layer has a thickness on trench bottom greater than trench sidewalls of said gate trench.

14. The super-junction trench MOSFET of claim 1, wherein said gate electrode is formed in an upper portion of said gate trench, a shielded electrode padded by a shielded insulation layer is formed in a lower portion of said gate trench and isolated from said gate electrode by an inter-insulation layer, said gate oxide layer has a thickness equal to or thinner than said shielded insulation layer on trench sidewalls of said gate trench.

15. The super-junction trench MOSFET of claim 1 further comprising a first type guard ring connected with said source region, and multiple second type guard rings having floating voltage in a termination area, wherein said first type guard ring and said multiple second type floating guard rings all have junction depths greater than said body region;

and said first type guard ring is connecting with a third doped column region of said second conductivity type and a fourth doped column region of said first conductivity type through a body region, said third doped column region and said fourth doped column region forming a second type charge balance area.

16. The super junction trench MOSFET of claim 15, wherein said third doped column region has about same column width as said second doped column region and said fourth doped column region has about half column width of said first doped column region in said unit cell.

17. The super-junction trench MOSFET of claim 1 further comprising a termination area comprising a second type charge balance area consists of a third doped column region of said second conductivity type and a fourth doped column region of said first conductivity type along a deep trench, and a channel stop region of said first conductivity type formed near the top surface of said epitaxial layer with a doping concentration higher than said epitaxial layer, wherein said channel stop region has a termination contact opening filled with said contact metal plug penetrating through said channel stop region, wherein a body contact region of said second conductivity type is formed surrounding at least bottom of said termination contact opening with a higher doping concentration than said body region, wherein an equal potential ring metal is covering said contact metal plug filled in said termination contact opening in said termination area.

18. The super junction trench MOSFET of claim 17, wherein said third doped column region has about same column width as said second doped column region and said fourth doped column region has about half column width of said first doped column region in said unit cell.