Method of forming a dual-trench field effect transistor

• US 8,829,641 B2
• Filed: 09/29/2010
• Issued: 09/09/2014
• Est. Priority Date: 01/30/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce D.
• Primary Examiner(s): WOLDEGEORGIS, ERMIAS T
• Application Number:
  US12/893,997
• Publication Number:
  US 20110014764A1
• Time in Patent Office: 1,441 Days
• Field of Search: 257/330, 257/339, 257/292, 257/331, 257/329, 257/239, 257/341, 257/342, 257/229, 257/328, 257/500, 257/E29.066, 257/E29.257, 438/206, 438/212, 438/270, 438/271, 438/E21.62, 438/E29.2, 438/E21.21, 438/E29.12, 438/243, 438/268, 438/316
• US Class Current: 257/500
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.

Claims

1. A method of forming a field effect transistor, comprising:

forming a well region in a semiconductor region of a first conductivity type, the well region being of a second conductivity type and having an upper surface and a lower surface;

forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region;

forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench;

forming a contiguous source region of the first conductivity type in the well region; and

filling the stripe trench, at least partially, with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region, the source region being in direct contact with the semiconductor material of the second conductivity type,

the source region being in contact with the gate trench and being in contact with a first sidewall of the stripe trench, the semiconductor material of the second conductivity type being contiguous between the first sidewall of the stripe trench and a second sidewall of the stripe trench.

2. The method of claim 1, wherein the stripe trench extends into the semiconductor region parallel to a current flow through the semiconductor region when the field effect transistor is in an on state.

3. The method of claim 1, wherein the stripe trench is entirely filled with the semiconductor material of the second conductivity type using selective epitaxial growth.

4. The method of claim 1, wherein the stripe trench is formed after the forming the gate trench and the forming the well region.

5. The method of claim 1, wherein the semiconductor region includes an epitaxial layer of the first conductivity type in which the well region is formed, the epitaxial layer has a thickness defined by a spacing between an upper surface and a lower surface of the epitaxial layer, the stripe trench extends into the epitaxial layer and terminates at a depth between one-half the thickness of the epitaxial layer and the lower surface of the epitaxial layer.

6. The method of claim 1, wherein the semiconductor region has a thickness defined by a vertical distance between an upper surface and a lower surface of the semiconductor region, the stripe trench terminates within a portion of the semiconductor region having a lower boundary at the lower surface of the semiconductor region and an upper boundary above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.

7. The method of claim 1, wherein the semiconductor region includes an epitaxial layer of the first conductivity type and a substrate of the first conductivity type, the substrate defines a drain contact region,

the method further comprising:

forming the epitaxial layer over the substrate, the well region being formed in the epitaxial layer, and the stripe trench and gate trench extending into and terminating within the epitaxial layer.

8. The method of claim 1, wherein the well region is in direct contact with the semiconductor material of the second conductivity type.

9. The method of claim 1, wherein the PN junction is at an interface between the semiconductor region and a sidewall of the stripe trench.