Three dimensional integrated circuits

• US 8,829,664 B2
• Filed: 07/12/2010
• Issued: 09/09/2014
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US12/834,077
• Publication Number:
  US 20110102014A1
• Time in Patent Office: 1,520 Days
• Field of Search: 257/686
• US Class Current: 257/686
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Claims

1. An integrated circuit comprising:

a substrate;

a first plurality of layers including a first programmable circuit;

a second plurality of layers including a plurality of programming circuits; and

a third plurality of layers including a second programmable circuit;

wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate;

wherein at least one of the first programmable circuit, the plurality of programming circuits, or the second programmable circuit is electrically coupled to at least one of the first programmable circuit, the plurality of programming circuits, or the second programmable circuit; and

wherein the first programmable circuit and the second programmable circuit are configured to be programmable by programming signals from the plurality of programming circuits.

2. The integrated circuit of claim 1, wherein the first programmable circuit comprises a logic circuit, wherein the plurality of programming circuits comprises a plurality of configuration circuits, and wherein the second programmable circuit comprises a routing circuit.

3. The integrated circuit of claim 2, wherein the logic circuit is programmable by the configuration circuits.

4. The integrated circuit of claim 2, wherein the routing circuit is programmable by the configuration circuits.

5. The integrated circuit of claim 2, wherein the third plurality of layers is located above the substrate, the first plurality of layers, and the second plurality of layers.

6. The integrated circuit of claim 2, wherein the second plurality of layers is located above the substrate, the first plurality of layers, and the third plurality of layers.

7. The integrated circuit of claim 1, further comprising:

a fourth plurality of layers including a third programmable circuit;

wherein at least one of the first programmable circuit, the plurality of programming circuits, the second programmable circuit, or the third programmable circuit is electrically coupled to at least one of the first programmable circuit, the plurality of programming circuit;

the second programmable circuit, or the third programmable circuit; and

wherein the first plurality of layers, the second plurality of layers, the third plurality of layers, and the fourth plurality of layers are formed in the stacked manner, which utilizes the plurality of integrated circuit fabrication masks, on the substrate.

8. The integrated circuit of claim 7, wherein the first programmable circuit comprises a logic circuit, wherein the plurality of programming circuits comprise a plurality of configuration circuits, wherein the second programmable circuit comprises a first routing circuit, and wherein the third programmable circuit comprises a second routing circuit.

9. The integrated circuit of claim 8, wherein the fourth plurality of layers is located above the substrate, the first plurality of layers, the second plurality of layers, and the third plurality of layers.

10. The integrated circuit of claim 9, wherein the third plurality of layers is located above the substrate and the first plurality of layers.

11. A method comprising:

forming an integrated circuit including a substrate, wherein said forming the integrated circuit comprises;

forming in a stacked manner that utilizes a plurality of integrated circuit fabrication masks on the substrate a first plurality of layers including a first programmable circuit;

forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a second plurality of layers including a plurality of programming circuits;

forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a third plurality of layers including a second programmable circuit, wherein the first programmable circuit and the second programmable circuit are configured to be programmable by programming signals from the plurality of programming circuits; and

electrically coupling at least one of the first programmable circuit, the plurality of programming circuits, or the second programmable circuit to at least one of the first programmable circuit, the plurality of programming circuits, or the second programmable circuit.

12. The method of claim 11, wherein the first programmable circuit comprises a logic circuit, wherein the plurality of programming circuits comprise a plurality of configuration circuits, and wherein the second programmable circuit comprises a routing circuit.

13. The method of claim 12, wherein the logic circuit is programmable by the configuration circuits.

14. The method of claim 12, wherein the routing circuit is programmable by the configuration circuits.

15. The method of claim 12, wherein the third plurality of layers is located above the substrate, the first plurality of layers, and the second plurality of layers.

16. The method of claim 12, wherein the second plurality of layers is located above the substrate, the first plurality of layers, and the third plurality of layers.

17. The method of claim 11, further comprising:

forming in the stacked manner that utilizes the plurality of integrated circuit fabrication masks on the substrate a fourth plurality of layers including a third programmable circuit; and

electrically coupling at least one of the first programmable circuit, the plurality of programming circuits, the second programmable circuit, or the third programmable circuit to at least one of the first programmable circuit, the plurality of programming circuits;

the second programmable circuit, or the third programmable circuit.

18. An integrated circuit comprising:

a substrate;

a first plurality of layers including a plurality of programmable logic circuits;

a second plurality of layers including a plurality of configuration circuits; and

a third plurality of layers including a plurality of programmable routing circuits;

wherein the first plurality of layers, the second plurality of layers, and the third plurality of layers are formed in a stacked manner, which utilizes a plurality of integrated circuit fabrication masks, on the substrate;

wherein at least one of the programmable logic circuits, the configuration circuits, or the programmable routing circuits is electrically coupled to at least one of the programmable logic circuits, the configuration circuits, or the programmable routing circuits;

wherein at least one programmable logic circuit is configured to be programmable by a first programming signal from at least one configuration circuit; and

wherein at least one programmable routing circuit is configured to be programmable by a second programming signal from at least one configuration circuit.

19. The integrated circuit of claim 18, wherein the third plurality of layers is located above the substrate, the first plurality of layers, and the second plurality of layers.

20. The integrated circuit of claim 18, wherein the second plurality of layers is located above the substrate, the first plurality of layers, and the third plurality of layers.