Current generator circuit and method for reduced power consumption and fast response

• US 8,829,882 B2
• Filed: 08/31/2010
• Issued: 09/09/2014
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Willey, Aaron
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US12/872,854
• Publication Number:
  US 20120049817A1
• Time in Patent Office: 1,470 Days
• Field of Search: 323/282, 323/285, 323/288, 323311-315, 323/317
• US Class Current: 323/315
• CPC Class Codes: G05F 3/20 using diode- transistor combinations G05F3/18 takes precedence
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

Current circuits, circuits configured to provide a bias voltage, and methods for providing a bias voltage are described, including a current circuit configured to receive a reference current and having an output at which an output current is provided. One such current circuit includes a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current. The current circuit further includes a second current mirror configured to receive a second portion of the reference current and receive the first current. The second current mirror is further configured to provide a portion of the first current to the output of the current circuit as the output current and to receive another portion of the first current and mirror the same as the second portion of the reference current.

Claims

1. A current circuit configured to receive a reference current and having an output at which an output current is provided, the current circuit comprising:

a first current mirror configured to receive a first portion of the reference current and further configured to mirror the first portion of the reference current to provide a first current; and

a second current mirror configured to receive a second portion of the reference current and coupled to the first current mirror to receive the first current, the second current mirror configured to provide a portion of the first current to the output of the current output current and further configured to receive another portion of the first current and mirror the same as the second portion of the reference current.

2. The current circuit of claim 1 wherein the sum of the first and second portions of the reference current is equal to the reference current.

3. The current circuit of claim 1 wherein the sum of the output current and the another portion of the first current is equal to the first current.

4. The current circuit of claim 1 wherein the second current mirror comprises:

a diode coupled first n-channel transistor configured to receive the first current; and

a second n-channel transistor having a gate coupled to a gate of the first n-channel transistor and configured to receive the second portion of the reference current.

5. The current circuit of claim 4 wherein the diode coupled first n-channel transistor has transistor dimensions different than transistor dimensions of the second n-channel transistor.

6. The current circuit of claim 4 wherein the first current mirror comprises:

an n-channel current mirror configured to receive the first portion of the reference current and mirror the same to provide an intermediate current; and

a p-channel current mirror configured to receive the intermediate current and mirror the same to provide the first current.

7. The current circuit of claim 6 wherein the p-channel current mirror comprises a diode coupled first p-channel transistor having a gate coupled to a gate of a second p-channel transistor, the second p-channel transistor having transistor dimensions different than transistor dimensions of the diode coupled first p-channel transistor.

8. The current circuit of claim 6 wherein the n-channel current mirror comprises first and second n-channel transistors, the first n-channel transistor diode coupled and having a gate coupled to a gate of the second n-channel transistor.

9. The current circuit of claim 8 wherein the n-channel transistors of the n-channel current mirror have different transistor dimensions.

10. The current circuit of claim 1, further comprising a capacitor coupled to the output of the current circuit.

11. A circuit configured to provide a bias voltage, the circuit comprising:

a capacitance having a node at which the bias voltage is provided;

a current source configured to provide a reference current;

a current subtraction stage coupled to the current source and configured to split the reference current into first and second currents, the first current adjusted responsive to the bias voltage and the second current based at least in part on the first current;

a current mirror stage coupled to the current subtraction stage to receive the second current and mirror the second current to provide a mirrored current;

a current output stage coupled to the current mirror stage to receive the mirrored current and having an output coupled to the capacitance, the current output stage configured to provide an output current to the capacitance based at least in part on the mirrored current and the bias voltage.

12. The circuit of claim 11 wherein the second current is based at least in part on a difference between the reference current and the first current.

13. The circuit of claim 11 wherein the current mirror stage comprises:

a first current mirror configured to mirror the second current to provide an intermediate current; and

a second current mirror coupled to the first current mirror and configured to mirror the intermediate current to provide the mirrored current.

14. The circuit of claim 13 wherein the first current mirror comprises:

a pair of n-channel transistors having gates coupled together, one of the n-channel transistors diode connected and configured to receive the second current; and

wherein the second current mirror comprises;

a pair of p-channel transistors having gates coupled together, one of the p-channel transistors diode connected and configured to receive the intermediate current.

15. The circuit of claim 11 wherein the current subtraction stage comprises:

a transistor coupled to the current source and having a gate coupled to the output of the current output stage.

16. The circuit of claim 11 wherein the current output stage comprises:

a diode coupled transistor configured to receive the mirrored current and having a gate coupled to the output of the current output stage.

17. The circuit of claim 11 wherein the current subtraction stage comprises a transistor coupled to the current source and having a gate coupled to the output of the current output stage and the current output stage comprises a diode coupled transistor configured to receive the mirrored current and having a gate coupled to the output of the current output stage, the diode coupled transistor of the current output stage having transistor dimensions greater than transistor dimensions of the transistor of the current subtraction stage.

18. A method for providing a bias voltage, comprising:

providing an output current having first and second current components, the sum of which equal to the output current, the first current component for charging or discharging a capacitance; and

adjusting the output current based at least in part on the second current component of the output current.

19. The method of claim 18 wherein adjusting the output current comprises:

increasing the output current responsive to a decrease in the second current component; and

decreasing the output current responsive to an increase in the second current component.

20. The method of claim 18 wherein providing the output current having first and second current components comprises:

dividing a reference current into first and second reference current components;

mirroring the first reference current component to provide the output current; and

adjusting the second reference current component responsive to the second current component of the output current.

21. The method of claim 20 wherein adjusting the second reference current component response to the second current component of the output current comprises mirroring the second current component of the output current to the second reference current component of the reference current.

22. The method of claim 20 wherein adjusting the output current comprises:

adjusting a ratio of the first and second reference current components responsive to the second current component of the output current.

23. The method of claim 20 wherein mirroring the first reference current component to provide the output current comprises:

mirroring the first reference current component to provide an intermediate current; and

mirroring the intermediate current to provide the output current.

24. The method of claim 18 wherein providing an output current having first and second current components comprises providing the output current to a diode coupled transistor, the capacitor coupled to a gate of the transistor.