Testing method for semiconductor integrated electronic devices and corresponding test architecture

• US 8,829,931 B2
• Filed: 10/04/2011
• Issued: 09/09/2014
• Est. Priority Date: 10/05/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto, Bard, Jean-Michel
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): Astacio-Oquendo, Giovanni
• Application Number:
  US13/252,895
• Publication Number:
  US 20120081137A1
• Time in Patent Office: 1,071 Days
• Field of Search: 324/750.01, 324/537, 324/763.01
• US Class Current: 324/750.01
• CPC Class Codes: G06F 11/26 Functional testing

Abstract

A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device. A testing architecture is also described for implementing this testing method.

Claims

1. A testing architecture, comprising:

a tester; and

a device associated with the tester and including;

a circuit to be tested; and

an integrated testing circuit coupled to the circuit to be tested, the integrated testing circuit including;

an interface configured to receive from the tester an expected response signal corresponding to a condition of correct operation of said circuit

a comparator configured to compare said expected response signal and an output response of said circuit; and

a test controller configured to generate a result having a first value in case of correspondence between said output response with said expected response signal, and a second value in case of non-correspondence between said output response and said expected response signal, wherein said integrated testing circuit comprises a decompression module and a compression module configured to compress an output signature of said output response and send the compressed output signature to the comparator, which is configured to compare the compressed output signature with said expected response signal.

2. The testing architecture according to claim 1, wherein the interface comprises an input decoder, an antenna, and a receiver, the input decoder being coupled to the antenna through the receiver, and said tester comprises a transmitter and an antenna configured to provide a wireless communication channel between said device and said tester.

3. The testing architecture according to claim 1, comprising a wired communication channel coupled between said tester and said device and configured to transmit information to said device through electrical signals.

4. The testing architecture according to claim 1, wherein the interface comprises:

a decoder that includes a high speed serial interface; and

a high speed digital input terminal coupled to the high speed serial interface and configured to receive information for said device.

5. The testing architecture according to claim 1, wherein the interface comprises a receiver configured to receive radiofrequency signals.

6. The testing architecture according to claim 1, wherein said integrated testing circuit comprises a result block configured to receive said result information.

7. The testing architecture according to claim 6, wherein said result block comprises at least one among:

a non-volatile memory element configured to store said result information;

a non-volatile FAMOS memory;

a fuse link;

an anti-fuse link;

a transmitter configured to communicate with a receiver of said interface and employ load modulation;

a transmitter coupled to the interface by a wireline and configured to employ a communication technique that varies an electric parameter of said wireline.

8. The testing architecture according to claim 1, wherein the device is one of a plurality of devices configured to communicate with said tester.

9. The testing architecture according to claim 1, wherein said circuit to be tested comprises one or more among:

digital circuits;

analog circuits;

RF circuits; and

MEMS circuits.

10. The testing architecture according to claim 1, wherein:

the device includes an analog circuit and a digital circuit that are electrically coupled to the integrated testing circuit, and the circuit to be tested is one of the analog circuit and digital circuit;

the interface is configured to receive from the tester the expected response signal corresponding to a condition of correct operation of one of said analog and digital circuits, provide a selection signal that selects one of the analog and digital circuits is to be tested, and provide a testing signal;

the device includes a selection circuit configured to provide the testing signal to the selected one of the analog and digital circuits; and

the comparator is configured to compare said expected response signal and the output response of said circuit.

11. A device configured to communicatively coupled with a tester, comprising:

a circuit to be tested;

an integrated testing circuit coupled to the circuit to be tested, the integrated testing circuit including;

an interface configured to receive from the tester an expected response signal corresponding to a condition of correct operation of said circuit;

a comparator configured to compare said expected response signal and an output response of said circuit; and

a test controller configured to generate a result information having a first value in case of correspondence between said output response with said expected response signal, and a second value in case of non-correspondence between said output response and said expected response signal, wherein said integrated testing circuit comprises a compression module configured to compress an output signature of said output response and send the compressed output signature to the comparator, which is configured to compare the compressed output signature with said expected response signal.

12. The device according to claim 11, wherein the interface comprises an input decoder, an antenna, and a receiver, the input decoder being coupled to the antenna through the receiver, said interface being configured to wirelessly receive information from the tester.

13. The device according to claim 11, wherein the interface is configured to receive information from the tester via a wired communication channel.

14. The device according to claim 11, wherein the interface comprises:

a decoder that includes a high speed serial interface; and

a high speed digital input terminal coupled to the high speed serial interface and configured to receive information from the tester.

15. The device according to claim 11, wherein the interface comprises a receiver configured to receive radiofrequency signals.

16. The device according to claim 11, wherein said integrated testing circuit comprises a storage device configured to store said result information.

17. The device according to claim 11, wherein:

the device includes an analog circuit and a digital circuit that are electrically coupled to the integrated testing circuit, and the circuit to be tested is one of the analog circuit and digital circuit;

the interface is configured to receive from the tester the expected response signal corresponding to a condition of correct operation of one of said analog and digital circuits, provide a selection signal that selects one of the analog and digital circuits is to be tested, and provide a testing signal;

the device includes a selection circuit configured to provide the testing signal to the selected one of the analog and digital circuits; and

the comparator is configured to compare said expected response signal and the output response of said circuit.