System incorporating power supply rejection circuitry and related method

• US 8,829,982 B2
• Filed: 07/09/2012
• Issued: 09/09/2014
• Est. Priority Date: 07/28/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mahadevan, Rajeevan, Pialis, Antonios, Wang, Robert, Yaghini, Navid, Karakiewicz, Rafal, Tang, Raymond Kwok Kei, Shen, Sida, Andruchow, Mark, Li, Zhuobin, Pantaleo, Nicola
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Kim, Jung H
• Application Number:
  US13/543,982
• Publication Number:
  US 20130027119A1
• Time in Patent Office: 792 Days
• Field of Search: 327/538, 327/530, 327/531, 327/532, 327/540, 327/541, 327/543, 327/551, 327/558, 327/156, 327/159
• US Class Current: 327/538
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A system and method providing power supply rejection. One embodiment provides for power supply rejection in PLL or DLL circuitry. First subcircuitry provides second subcircuitry a supply voltage which is a filtered version of power from an external source. The first subcircuitry includes a first field effect transistor and a first low pass filter coupled to receive a signal from the external power source during operation of the second subcircuitry. The filter is coupled to provide a filtered version of the power source signal to the gate of the first transistor, so that when a first source/drain region of the first transistor is connected to receive power from the external source and the gate of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power received from the external source.

Claims

1. An electronic system including:

a first subcircuitry;

a second subcircuitry, and

a phase locked loop (PLL),

wherein the first subcircuitry positioned to provide a supply voltage, V_DD, as a filtered version of power, P_V, available from an external power source, to the second subcircuitry, wherein the first subcircuitry is separate from the second subcircuitry,

wherein the first subcircuitry comprises;

a first transistor having first and second source/drain regions and a gate region; and

a first low pass filter coupled to receive a power source signal from the external power source during operation of the second subcircuitry,

wherein the first low pass filter is also coupled to provide a filtered version of the power source signal to the gate region of the first transistor, so that when the first source/drain region of the first transistor is coupled to receive power from the external power source and the gate region of the first transistor receives the filtered version of the power source signal, the second source/drain region of the first transistor provides a first modified version of the power, P_V, received from the external power source,

wherein the second subcircuitry includes;

a second transistor directly coupled in series with the first transistor,

wherein the first and second transistors are of a same conductivity type, wherein the second transistor has first and second source/drain regions and a gate region, wherein the first source/drain region of the second transistor is coupled to the first transistor, and wherein the second source/drain region of the second transistor is coupled to a power node of the PLL;

wherein the first source/drain region of the second transistor is coupled to receive the first modified version of the power, P_v, received from the external power source;

wherein the electronic system further comprises;

a first resistor; and

a second low pass filter coupled in series with the first resistor to receive a signal from the external power source during operation of the second subcircuitry, wherein the second low pass filter is coupled to provide a second filtered version of the power source signal to the gate region of the second transistor, so that when the first source/drain region of the first transistor receives power, P_v, from the external power source and the second low pass filter provides the second filtered version of the power source signal to the gate region of the second transistor, the second source/drain region of the second transistor provides a second modified version of the power, P_V, in accord with application of the second filtered version of the power source signal to the gate region of the second transistor.

2. The electronic system of claim 1 wherein, when the first transistor is coupled to receive power from the external power source and the gate region of the first transistor receives the filtered version of the power source signal, the first modified version of the power, P_v, received from the external power source is provided to the second subcircuitry as the supply voltage V_DD.

3. The electronic system of claim 1, wherein the second subcircuitry is coupled to receive the second modified version of the power, P_V.

4. The electronic system of claim 1, wherein the second filtered version of the power source signal provides the gate region of the second transistor with a gate voltage which provides power supply rejection above a cut-off frequency determined in part by filter characteristics.

5. The electronic system of claim 1 further including:

a second resistor coupled in series with the first resistor, the first and second resistors positioned between a reference terminal V_SS and a connection for receiving the power, P_V, when the power is made available from the external power source, the second resistor limiting current flow to the reference terminal V_SS when the first source/drain region of the first transistor is coupled to receive the power P_V.

6. The electronic system of claim 1, wherein the power node provides power supply to the PLL, and wherein the PLL comprises:

control and interface circuitry,

fast integral path circuitry,

control circuitry,

slow integral circuit path circuitry, and

proportional path circuitry.

7. The electronic system of claim 1 further comprises a serialization or deserialization circuitry coupled to the PLL.

8. The electronic system of claim 7, wherein the PLL includes:

a fast integral path circuitry,

a slow integral circuit path circuitry, and

a proportional path circuitry.

9. An apparatus comprising:

a first transistor having a gate terminal;

a second transistor coupled in series to the first transistor, the second transistor having a gate terminal, wherein the first and second transistors are of the same conductivity type;

a first low pass filter (LPF) to receive a power source signal from a power source and to provide a filtered version of the power source signal to the gate terminal of the first transistor; and

a second LPF to receive a voltage divided version of the power source signal and to provide a filtered version of the voltage divided version of the power source signal to the gate terminal of the second transistor.

10. The apparatus of claim 9, wherein the first and second transistors are p-type transistors.

11. The apparatus of claim 9 further comprises a first resistor having a first terminal coupled to a node to receive the power source signal, and second terminal coupled to an input of the second LPF.

12. The apparatus of claim 11 further comprises a second resistor having a first terminal coupled the input of the second LPF, and a second terminal coupled to ground.

13. The apparatus of claim 9 further comprises:

a first resistor; and

a second resistor coupled in series with the first resistor, the first and second resistors forming a voltage divider to provide the voltage divided version of the power source signal to the second LPF.

14. The apparatus of claim 9, wherein the first transistor having a source terminal coupled to a node which receives the power source signal.

15. The apparatus of claim 9, wherein the second transistor having a drain terminal to provide an output power supply signal to a load.

16. The apparatus of claim 15, wherein the load is phase locked loop (PLL).