Display panel

• US 8,830,439 B2
• Filed: 04/21/2011
• Issued: 09/09/2014
• Est. Priority Date: 06/10/2010
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Asako, Isao, Nakagawa, Yukinori, Nishino, Hiromi, Shimada, Shinji
• Primary Examiner(s): Duong, Thoi
• Application Number:
  US13/702,749
• Publication Number:
  US 20130077009A1
• Time in Patent Office: 1,237 Days
• Field of Search: 349/86, 349/110, 349/138, 349/42, 349/155, 349/156, 349/43, 349/88
• US Class Current: 349/155
• CPC Class Codes: G02F 1/1334 based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells

Abstract

Provided is a display panel using polymer network liquid crystal in which a monomer unreacted region is reduced and a thin-film transistor can be prevented from being irradiated with light energy. In the display panel, a black matrix (22a) is provided as an element having a light-shielding property in a first substrate (2a), a pixel electrode (37) and a thin-film transistor (32) serving as a switching element for driving the pixel electrode (37) are provided in a second substrate (3a), polymer network liquid crystal (11) is filled between the first substrate (2a) and the second substrate (3a), a cover portion (221) that is part of the black matrix (22a) provided in the first substrate (2a) faces the thin-film transistor (32) provided in the second substrate (3a), and the outer periphery of the cover portion (221) is located outside the outer periphery of a channel region by a specified dimension or more.

Claims

1. A display panel, comprising:

a first substrate and a second substrate, the first substrate having a light-shielding element, the second substrate having a pixel electrode and a thin film transistor that drives the pixel electrode,

wherein the first substrate and the second substrate are disposed to face each other having a gap therebetween, and a polymer network liquid crystal is filled between the first substrate and the second substrate, and

wherein the light-shielding element is disposed in a location that faces the thin film transistor, and an outer periphery of the light-shielding element is located outside an outer periphery of a channel region of the thin film transistor at a distance of at least 10 μ

m greater than a sum of “

a length of the channel region,”

“

a height of a surface of an uppermost layer in the second substrate from a surface of the channel region,” and

“

a thickness of the polymer network liquid crystal,”

when viewed from a direction that is perpendicular to a plane direction of the first substrate and the second substrate.

2. The display panel according to claim 1, wherein the first substrate is provided with first spacers that define a gap between the first substrate and the second substrate, and

wherein a total cross-sectional area of the first spacers and an area of a region filled with the polymer network liquid crystal are set so as to satisfy:

(the total cross-sectional area of the first spacers)/(the area of the region filled with the polymer network liquid crystal) =0.001 to 0.017.

3. The display panel according to claim 2, wherein the first substrate is provided with second spacers that are shorter than the first spacers.

4. The display panel according to claim 3, wherein a height difference between the first spacers and the second spacers is 0.1 to 1.0 μ

m.

5. The display panel according to claim 1, wherein the first substrate is provided with a spacer that defines a gap between the first substrate and the second substrate, and the spacer is formed so as to overlap substantially the entire light-shielding element in a portion that is located in a region filled with the polymer network liquid crystal.

6. The display panel according to claim 5, wherein the spacer has higher portions and lower portions.

7. The display panel according to claim 6, wherein a total cross-sectional area of the higher portions of the spacer and an area of the region filled with the polymer network liquid crystal are set so as to satisfy:

(the total cross-sectional area of the higher portions of the spacer)/(the area of the region filled with the polymer network liquid crystal) =0.001 to 0.017.

8. The display panel according to claim 7, wherein a height difference between the higher portions and the lower portions is 0.1 to 1.0 μ

m.

9. A display panel, comprising:

a first substrate and a second substrate disposed to face each other having a gap therebetween;

spacers formed in the first substrate, the spacers defining the gap between the first substrate and the second substrate;

a pixel electrode and a thin film transistor formed in the second substrate, the thin film transistor driving the pixel electrode; and

a polymer network liquid crystal filled between the first substrate and the second substrate,

wherein the spacers has a light-shielding property, and each disposed in a location that faces the thin film transistor, and an outer periphery of each of the spacers is located outside an outer periphery of a channel region of the thin film transistor at a distance of at least 10μ

m greater than a sum of “

a length of the channel region,”

“

a height of a surface of an uppermost layer in the second substrate from a surface of the channel region,” and

“

a thickness of the polymer network liquid crystal,”

when viewed from a direction that is perpendicular to a plane direction of the first substrate and the second substrate.

10. The display panel according to claim 9, wherein the spacers include first spacers and second spacers that are shorter than the first spacers.

11. The display panel according to claim 10, wherein a total cross-sectional area of the first spacers and an area of the region filled with the polymer network liquid crystal are set so as to satisfy:

(the total cross-sectional area of the first spacers)/(the area of the region filled with the polymer network liquid crystal) =0.001 to 0.017.

12. The display panel according to claim 10, wherein a height difference between the first spacers and the second spacers is 0.1 to 1.0 μ

m.

13. A display panel, comprising:

a first substrate and a second substrate disposed to face each other having a gap therebetween;

a spacer that has a light-shielding property and that borders pixels in the first substrate, the spacer defining the gap between the first substrate and the second substrate;

a pixel electrode and a thin film transistor formed in the second substrate, the thin film transistor driving the pixel electrode; and

a polymer network liquid crystal filled between the first substrate and the second substrate,

wherein the spacer has a portion that faces the thin film transistor, and an outer periphery of the portion that faces the thin film transistor is located outside an outer periphery of a channel region of the thin film transistor at a distance of at least 10μ

m greater than a sum of “

a length of the channel region,”

“

a height of a surface of an uppermost layer in the second substrate from a surface of the channel region,” and

“

a thickness of the polymer network liquid crystal,”

when viewed from a direction that is perpendicular to a plane direction of the first substrate and the second substrate.

14. The display panel according to claim 13, wherein the spacer has higher portions and lower portions.

15. The display panel according to claim 14, wherein a total cross-sectional area of the higher portions of the spacer and an area of the region filled with the polymer network liquid crystal are set so as to satisfy:

(the total cross-sectional area of the higher portions)/(the area of the region filled with the polymer network liquid crystal) =0.001 to 0.017.

16. The display panel according to claim 14, wherein a height difference between the higher portions and the lower portions is 0.1 to 1.0 μ

m.