Method and apparatus for switching clock frequency in a system-in-package device

• US 8,831,160 B2
• Filed: 01/17/2013
• Issued: 09/09/2014
• Est. Priority Date: 01/30/2012
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Urzi, Ignazio Antonino, Ferris, Andrew
• Primary Examiner(s): Singh, Hirdepal
• Application Number:
  US13/744,146
• Publication Number:
  US 20130195235A1
• Time in Patent Office: 600 Days
• Field of Search: 375/215, 375/286, 375/295, 375/306, 375/309, 375/326, 375/339, 375/354, 375/362, 375/377
• US Class Current: 375/362
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04L 7/00 Arrangements for synchronising receiver with transmitter synchronisation of generators of electric oscillations or pulses H03L7/00
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made.

Claims

1. An apparatus, comprising:

a first clock source;

a second clock source; and

circuitry configured to supply a clock signal to a circuit, said circuitry configured to change the clock signal from one frequency to another different frequency such that no clock signal is supplied when changing from said one frequency to said another different clock frequency;

wherein said circuitry comprises;

a first delay chain clocked at one of said frequency or different frequency and having a plurality of taps;

a logic circuit coupled to the taps of the first delay chain and configured to generate a first control signal indicating to stop use of said frequency and generate a second control signal enabling frequency change for said clock signal; and

a second delay chain clocked at one of said frequency or different frequency and reset in response to said first control signal and having an output configured to generate a third control signal indicating to start use of said different frequency.

2. An apparatus as claimed in claim 1, wherein said second clock source is configured to provide a first frequency clock signal and a second frequency clock signal.

3. An apparatus as claimed in claim 2, wherein said circuitry is configured to change said clock signal supplied from said first frequency clock signal to said second frequency clock signal by stopping the supply of the first clock signal to said circuit, providing a clock signal from said first clock source to said circuit, stopping the supply of the clock signal from said first clock source and providing said second frequency clock signal.

4. An apparatus as claimed in claim 1, wherein said second clock source comprises a phase lock loop.

5. An apparatus as claimed in claim 4, wherein said second clock source is configured to attain lock when said clock signal from the first clock source is being supplied to said circuit.

6. An arrangement as claimed in claim 1, comprising delay locked loop circuitry configured to provide a controllable delay, said delay locked loop circuitry configured to be reconfigured while said circuit uses said first clock.

7. An apparatus as claimed in claim 6, wherein said delay locked loop circuitry comprises a programmable delay through which a clock signal is selectively controlled to pass.

8. An apparatus as claimed claim 1, wherein said circuitry is configured to change a clock signal at said one frequency determined by one of said first and second clock sources to a clock signal at said another frequency determined by the other of said first and second clock sources.

9. An apparatus as claimed in claim 1, wherein said first clock source comprises an oscillator.

10. An apparatus as claimed in claim 1, wherein said circuitry comprises a circuit for transmitting data.

11. An apparatus as claimed in claim 10, wherein said circuitry for transmitting data comprises a plurality of bit slices for respective bits of data and at least one bit slice for a clock to be transmitted with said data, said bit slices being substantially the same.

12. An apparatus as claimed in claim 1, wherein said circuitry comprises gating circuitry configured to receive a clock signal and an enable signal and having an output, said gating circuitry configured to provide said clock signal on an output.

13. An apparatus as claimed in claim 12, wherein said circuitry comprises a delay chain having a plurality of taps and wherein said enable signal is dependent on an output of said delay chain.

14. An apparatus as claimed in claim 1, where said circuitry is configured to retain data when no clock signal is supplied such that said data is present when said clock signal is reapplied.

15. An apparatus as claimed in claim 1, wherein said circuitry is configured to receive a reset signal when no clock signal is supplied, said circuit being configured to be reset when no clock signal is applied.

16. An apparatus as claimed in claim 1, wherein the apparatus is implemented on an integrated circuit die.

17. An apparatus as claimed in claim 16, further comprising a second integrated circuit die coupled for communication with said integrated circuit die.

18. An apparatus as claimed in claim 17, wherein said integrated circuit die comprises a processor and said second integrated circuit die comprises a memory configured to store boot data for said processor.

19. An apparatus as claimed in claim 18, wherein said integrated circuit die is configured to communicate with said second integrated circuit die at a clock frequency dependent on a clock frequency of said first clock circuit during a boot operation.

20. An apparatus, comprising:

a transmit physical interface including a data output and a clock output which is a timing reference for the data output;

a first oscillating circuit configured to generate a first clock signal having a variable frequency;

a second oscillating circuit configured to generate a second clock signal at a fixed frequency; and

a control circuit configured to control operation of the transmit physical interface during a change in frequency of the clock output, said control circuit operable to;

terminate transmit physical interface data output with the clock output derived from the first clock signal;

activate transmit physical interface data output with the clock output derived from the second clock signal;

change frequency of the first clock signal;

terminate transmit physical interface data output with the clock output derived from the second clock signal; and

activate transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.

21. The apparatus of claim 20, further including a delay lock loop circuit configured to control a phase of the clock output;

and

wherein the control circuit is further operable to wait for said delay lock loop circuit to lock on said changed frequency before terminating transmit physical interface data output with the clock output derived from the second clock signal and then activating the transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.

22. The apparatus of claim 21, wherein said second oscillating circuit is a phase lock look circuit;

and

wherein the control circuit is further operable to wait for said delay lock loop circuit and phase lock loop circuit to lock before terminating transmit physical interface data output with the clock output derived from the second clock signal and then activating the transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.

23. The apparatus of claim 20, where said transmit physical interface is configured to retain data in the absence of the first and second clock signals such that said data is present when one of said first and second clock signal is available.

24. The apparatus of claim 20, wherein said transmit physical interface comprises:

a plurality of bit slices configured to store respective bits of data; and

at least one bit slice configured to store clock data.

25. A method, comprising:

transmitting data output from a transmit physical interface with a clock output derived from a first clock signal having a variable frequency; and

in response to a need to change a frequency of the clock output;

terminating transmission of data output from the transmit physical interface with the clock output derived from the first clock signal;

activating transmission of data output from the transmit physical interface with the clock output derived from a second clock signal having a fixed frequency;

changing a frequency of the first clock signal;

terminating transmission of data output from the transmit physical interface data output with the clock output derived from the second clock signal; and

activating transmission of data output from the transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.

26. The method of claim 25, further comprising:

controlling a phase of the clock output with a delay lock loop circuit; and

waiting for said delay lock loop circuit to lock on said changed frequency before terminating transmission of data output from the transmit physical interface data output with the clock output derived from the second clock signal and activating transmission of data output from the transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.

27. The method of claim 26, further comprising:

generating said second clock signal with a phase lock look circuit; and

waiting for said delay lock loop circuit and phase lock loop circuit to lock before terminating transmission of data output from the transmit physical interface data output with the clock output derived from the second clock signal and activating transmission of data output from the transmit physical interface data output with the clock output derived from the first clock signal at the changed frequency.