Use of host system resources by memory controller

• US 8,832,354 B2
• Filed: 03/22/2010
• Issued: 09/09/2014
• Est. Priority Date: 03/25/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sokolov, Dotan, Rotbard, Barak
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Perez-Velez, Rocio Del Mar
• Application Number:
  US12/728,287
• Publication Number:
  US 20100250836A1
• Time in Patent Office: 1,632 Days
• Field of Search: 711/103, 711/104
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Claims

1. A method for data storage, comprising:

in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple memory cells;

allocating a portion of the host memory for use by the memory controller;

sending a storage request, by the memory controller to the host, instructing the host to store, in the allocated portion of the host memory, information items relating to respective groups of the memory cells of the non-volatile memory;

storing, by the host, in the allocated portion of the host memory, the information items relating to the respective groups of the memory cells responsive to the storage request sent by the memory controller;

receiving, by the memory controller, from the host a command that causes the memory controller to access a given group of the memory cells;

sending, in response to the command, a retrieval request, by the memory controller to the host processor, instructing the host to retrieve from the allocated portion of the host memory by the memory controller a respective information item relating to the given group of the memory cells;

retrieving, by the host, from the allocated portion of the host memory, the information items relating to the respective groups of the memory cells responsive to the retrieval request sent by the memory controller; and

accessing the given group of the memory cells using the retrieved information item.

2. The method according to claim 1, wherein the host memory comprises a Random Access Memory (RAM).

3. The method according to claim 1, wherein the information items comprise read thresholds, and wherein accessing the given group comprises reading the memory cells in the group using one or more read thresholds retrieved from the host memory.

4. The method according to claim 1, wherein the information items comprise erase thresholds, and wherein accessing the given group comprises erasing the memory cells in the given group using one or more erase thresholds retrieved from the host memory.

5. The method according to claim 1, wherein the memory cells are programmed using a programming process, wherein the information items comprise parameters of the programming process, and wherein accessing the given group comprises programming the given group using one or more of the parameters that are retrieved from the host memory.

6. The method according to claim 5, wherein the programming process comprises an iterative Programming and Verification (P&

V) process.

7. The method according to claim 1, wherein the information items are indicative of wear levels of the respective groups of the memory cells.

8. The method according to claim 1, wherein the information items are indicative of distortion levels in the respective groups of the memory cells.

9. The method according to claim 1, wherein the information items specify at least one attribute selected from a set of attributes consisting of a number of programming states, an Error Correction Code (ECC) and an ECC block size to be used in programming the respective groups of the memory cells.

10. The method according to claim 1, wherein the information items specify a relation between logical addresses and physical storage locations of the respective groups of the memory cells.

11. The method according to claim 1, wherein the information items are indicative of data stored in memory cells that neighbor the respective groups of the memory cells.

12. The method according to claim 1, wherein the common physical interface conforms to one of a NAND interface specification, a Micro-SD (μ

SD) interface specification, an Embedded Multi-Media Card (eMMC) interface specification, a Universal Flash Storage (UFS) interface specification, a Serial Advanced Technology Attachment (SATA) interface specification, a Universal Serial Bus (USB) interface specification and a Peripheral Component Interconnect (PCI) interface.

13. The method according to claim 1, wherein the sending of a storage request, by the memory controller, to the host, comprises sending a signal on a hardware connection from the memory controller to the host.

14. The method according to claim 1, wherein the sending, in response to the command, a retrieval request, by the memory controller, to the host comprises sending a signal on a hardware connection from the memory controller to the host.

15. The method according to claim 1, further comprising allocating another portion of the host memory to store program instructions and data.

16. A data storage apparatus, comprising:

a first interface, which is configured to communicate with a non-volatile memory that includes multiple memory cells;

a second interface, which is configured to communicate with a host having a host memory, wherein the host is configured to allocate a portion of the host memory for use by the data storage apparatus; and

a processor, which is configured to;

send a request to the host, instructing the host to store in the allocated portion of the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory;

receive from the host a command that causes the processor to access a given group of the memory cells;

send, in response to the command, a retrieval request to the host, instructing the host to retrieve from the allocated portion of the host memory a respective information item relating to the given group of the memory cells;

receive from the host the retrieved information item relating to the given group of the memory cells; and

access the given group of the memory cells using the retrieved information item.

17. The apparatus according to claim 16, wherein the host memory comprises a Random Access Memory (RAM).

18. The apparatus according to claim 16, wherein the information items comprise read thresholds, and wherein the processor is configured to read the memory cells in the given group using one or more read thresholds retrieved from the host memory.

19. The apparatus according to claim 16, wherein the information items comprise erase thresholds, and wherein the processor is configured to erase the memory cells in the given group using one or more erase thresholds retrieved from the host memory.

20. The apparatus according to claim 16, wherein the memory cells are programmed using a programming process, wherein the information items comprise parameters of the programming process, and wherein the processor is configured to program the given group using one or more of the parameters that are retrieved from the host memory.

21. The apparatus according to claim 20, wherein the programming process comprises an iterative Programming and Verification (P&

V) process.

22. The apparatus according to claim 16, wherein the information items are indicative of wear levels of the respective groups of the memory cells.

23. The apparatus according to claim 16, wherein the information items are indicative of distortion levels in the respective groups of the memory cells.

24. The apparatus according to claim 16, wherein the information items specify at least one attribute selected from a set of attributes consisting of a number of programming states and, Error Correction Code (ECC) and an ECC block size to be used in programming the respective groups of the memory cells.

25. The apparatus according to claim 16, wherein the information items specify a relation between logical addresses and physical storage locations of the respective groups of the memory cells.

26. The apparatus according to claim 16, wherein the information items are indicative of data stored in memory cells that neighbor the respective groups of the memory cells.

27. The apparatus according to claim 16, wherein the second interface conforms to one of a NAND interface specification, a Micro-SD (μ

SD) interface specification, an Embedded Multi-Media Card (eMMC) interface specification, a Universal Flash Storage (UFS) interface specification, a Serial Advanced Technology Attachment (SATA) interface specification, a Universal Serial Bus (USB) interface specification and a Peripheral Component Interconnect (PCI) interface.

28. The apparatus according to claim 16, wherein the processor is further configured to use a hardware signal to send the storage request to the host.

29. The apparatus according to claim 16, wherein the processor is further configured to use a hardware signal to send the retrieval request to the host.

30. The apparatus according to claim 16, wherein the host is further configured to allocate another portion of the host memory to store program instructions and data.

31. A data storage apparatus, comprising:

a non-volatile memory comprising multiple memory cells; and

a processor, which is configured to;

communicate with a host having a host memory, wherein the host is configured to allocate a portion of the host memory for use by the data storage apparatus;

send a storage request to the host, instructing the host to store in the host memory information items relating to respective groups of the memory cells of the non-volatile memory;

receive from the host a command that causes the processor to access a given group of the memory cells;

send, in response to the command, a retrieval request to host, instructing the host to retrieve from the host memory a respective information item relating to the given group of the memory cells;

receive from the host, the retrieved information item relating to the given group of the memory cells; and

access the given group of the memory cells using the retrieved information item.

32. The apparatus according to claim 31, wherein the host is further configured to allocate another portion of the host memory to store program instructions and data.