Solid state storage device controller with expansion mode

• US 8,832,360 B2
• Filed: 05/24/2013
• Issued: 09/09/2014
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Klein, Dean
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/901,806
• Publication Number:
  US 20140013035A1
• Time in Patent Office: 473 Days
• Field of Search: 711/2, 711/103, 711/154
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Claims

1. A solid state storage device comprising:

a memory device of a first type;

a first memory device of a second type different than the first type;

a second memory device of the second type;

a plurality of first communication channels, with a first portion of the plurality of first communication channels coupled to the memory device of the first type and a second portion of the plurality of first communication channels coupled to the first memory device of the second type;

a plurality of second communication channels separate from the plurality of first communication channels and coupled to the second memory device of the second type; and

a multiplexer coupled to receive output from a plurality of memory sequencers and to provide output of a selected one of the plurality of memory sequencers to the plurality of first communication channels, wherein the plurality of memory sequencers comprises a memory sequencer for memory devices of the first type and a memory sequencer for memory devices of the second type.

2. The solid state storage device of claim 1, wherein the first type of memory device has a slower access time than the second type of memory device.

3. The solid state storage device of claim 1, wherein the first type of memory device is a non-volatile memory device and the second type of memory device is a volatile memory device.

4. The solid state storage device of claim 1, wherein the memory sequencer for memory devices of the second type is further coupled to provide output to the plurality of second communication channels.

5. The solid state storage device of claim 4, further comprising:

wherein the second portion of the plurality of first communication channels is coupled to selectively receive data for the first memory device of the second type from the memory sequencer for memory devices of the second type;

wherein a first portion of the plurality of second communication channels is coupled to receive control signals for the first memory device of the second type and the second memory device of the second type from the memory sequencer for memory devices of the second type; and

wherein a second portion of the plurality of second communication channels is coupled to receive data for the second memory device of the second type from the memory sequencer for memory devices of the second type.

6. The solid state storage device of claim 5, wherein the second portion of the plurality of first communication channels is a single first communication channel.

7. The solid state storage device of claim 1, wherein the memory sequencer for memory devices of the second type is a first memory sequencer for memory devices of the second type, and further comprising:

a second memory sequencer for memory devices of the second type;

wherein the plurality of second communication channels are coupled to receive control signals and data for the second memory device of the second type from the second memory sequencer for memory devices of the second type.

8. The solid state storage device of claim 7, further comprising:

wherein the second portion of the plurality of first communication channels is coupled to selectively receive control signals and data for the first memory device of the second type from the first memory sequencer for memory devices of the second type.

9. The solid state storage device of claim 8, wherein the second portion of the plurality of first communication channels is two first communication channels.

10. The solid state storage device of claim 1, wherein the memory device of the first type further comprises a plurality of memory devices of the first type, wherein each memory device of the first type is coupled to receive control signals and data from one first communication channel of the plurality of first communication channels not contained within the second portion of the plurality of first communication channels.

11. The solid state storage device of claim 10, wherein more than one memory device of the first type is coupled to receive control signals and data from one first communication channel of the plurality of first communication channels.

12. The solid state storage device of claim 1, wherein the plurality of memory sequencers further comprises one or more additional memory sequencers for memory devices of the first type.

13. A solid state storage device comprising:

a memory device of a first type;

a first memory device of a second type different than the first type;

a second memory device of the second type;

a memory sequencer for memory devices of the first type;

a memory sequencer for memory devices of the second type;

a plurality of first communication channels, with a first portion of the plurality of first communication channels coupled to the memory device of the first type and a second portion of the plurality of first communication channels coupled to the first memory device of the second type;

a plurality of second communication channels separate from the plurality of first communication channels and coupled to provide output from the memory sequencer for memory devices of the second type to the second memory device of the second type; and

a multiplexer coupled to receive output from a plurality of memory sequencers and to provide output of a selected one of the plurality of memory sequencers to the plurality of first communication channels, wherein the plurality of memory sequencers comprises the memory sequencer for memory devices of the first type and the memory sequencer for memory devices of the second type.

14. The solid state storage device of claim 13, wherein the first type of memory device is a non-volatile memory device and the second type of memory device is a volatile memory device.

15. The solid state storage device of claim 13, further comprising:

wherein the first memory device of the second type is coupled to receive control signals from the memory sequencer for memory devices of the second type through a first portion of the plurality of second communication channels, and to selectively receive data from the memory sequencer for memory devices of the second type through the second portion of the plurality of first communication channels; and

wherein the second memory device of the second type is coupled to receive control signals from the memory sequencer for memory devices of the second type through the first portion of the plurality of second communication channels, and to receive data from the memory sequencer for memory devices of the second type through a second portion of the plurality of second communication channels.

16. The solid state storage device of claim 15, wherein the memory device of the first type is coupled to selectively receive control signals and data through the first portion of the plurality of first communication channels.

17. The solid state storage device of claim 16, wherein the first portion of the plurality of first communication channels is a single first communication channel, wherein the second portion of the plurality of first communication channels is a single first communication channel, wherein the first portion of the plurality of second communication channels is a single second communication channel, and wherein the second portion of the plurality of second communication channels is a single second communication channel.

18. The solid state storage device of claim 13, wherein the memory device of the first type further comprises a plurality of memory devices of the first type arranged in groups, wherein each group of memory devices of the first type is coupled to receive control signals and data from a corresponding first communication channel of the plurality of first communication channels not contained within the second portion of the plurality of first communication channels.

19. A solid state storage device comprising:

a memory device of a first type;

a first memory device of a second type different than the first type;

a second memory device of the second type;

a memory sequencer for memory devices of the first type;

a first memory sequencer for memory devices of the second type;

a second memory sequencer for memory devices of the second type;

a plurality of first communication channels, with a first portion of the plurality of first communication channels coupled to the memory device of the first type and a second portion of the plurality of first communication channels coupled to the first memory device of the second type;

a plurality of second communication channels separate from the plurality of first communication channels and coupled between the second memory device of the second type and the first memory sequencer for memory devices of the second type; and

a multiplexer coupled to receive output from a plurality of memory sequencers and to provide output of a selected one of the plurality of memory sequencers to the plurality of first communication channels, wherein the plurality of memory sequencers comprises the memory sequencer for memory devices of the first type and the second memory sequencer for memory devices of the second type.

20. The solid state storage device of claim 19, wherein the first type of memory device is a non-volatile memory device and the second type of memory device is a volatile memory device.

21. The solid state storage device of claim 19, wherein the plurality of second communication channels are coupled to receive control signals and data for the second memory device of the second type from the first memory sequencer for memory devices of the second type.

22. The solid state storage device of claim 21, wherein the second portion of the plurality of first communication channels is coupled to selectively receive control signals and data for the first memory device of the second type from the second memory sequencer for memory devices of the second type.

23. The solid state storage device of claim 22, wherein the second portion of the plurality of first communication channels is two first communication channels.